MC68LC040RC25A Datasheet, PDF (199/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
7.8.2.4 M68040 ASYNCHRONOUS DMA ARBITRATION. Figure 7-38 illustrates a
sample synchronizer circuit. Figure 7-39 illustrates how an M68040 can be implemented
to simulate an MC68030. The synchronizer circuit has an output indicating whether or not
a signal has been asserted for at least two consecutive rising edges of BCLK. If the
synchronizer circuit indicates that the input has not been stable for at least two clocks,
then the processor and alternate bus master stay in the current state. Figure 7-37(a)
duplicates the MC68030 implementation of the bus arbitration circuitry in which the
M68040 is allowed to yield the bus only after the indeterminate condition has been
eliminated. Figure 7-37(b) is similar to the MC68030 implementation except that the DMA
device has lower priority and can only perform transfers when the M68040 is in the idle
state. In either case, the M68040 is the default bus master; therefore, if there are no
pending requests from either device, the external bus arbiter gives the bus to the M68040.
RV
ABR
R
CLK
AV
ABGACK
A
CLK
Figure 7-38. Sample Synchronizer Circuit
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