MC68LC040RC25A Datasheet, PDF (57/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

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the logical addresses of the currently executing process. Portions of translation tables can
be dynamically allocated as the process requires additional memory.
ROOT POINTER
FIRST
LEVEL
ROOT
TABLES
SECOND
LEVEL
POINTER
TABLES
THIRD
LEVEL
PAGE
TABLES
Figure 3-7. Translation Table Structure
The current privilege mode determines the use of the URP or SRP for translation of the
access. The root pointer contains the base address of the translation table’s root-level
table. The translation table consists of tables of descriptors. The table descriptors of the
root- and pointer-levels can be either resident or invalid. The page descriptors of the page-
level table can be resident, indirect, or invalid. A page descriptor defines the physical
address of a page frame in memory that corresponds to the logical address of a page. An
indirect descriptor, which contains a pointer to the actual page descriptor, can be used
when two or more logical addresses access a single page descriptor.
The table search uses logical addresses to access the translation tables. Figure 3-8
illustrates a logical address format, which is segmented into four fields: root index (RI),
pointer index (PI), page index (PGI), and page offset. The first three fields extracted from
the logical address index the base address for each table level. The seven bits of the
logical address RI field are multiplied by 4 or shifted to the left by two bits. This sum is
concatenated with the upper 23 bits of the appropriate root pointer (URP or SRP) to yield
the physical address of a root-level table descriptor. Each of the 128 root-level table
descriptors corresponds to a 32-Mbyte block of memory and points to the base of a
pointer-level table.
3-8
M68040 USER'S MANUAL
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