MC68LC040RC25A Datasheet, PDF (259/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
The following tie-case example illustrates how the 67-bit mantissa allows the FPU to meet
the error bound of the IEEE specification:
Result
Intermediate
Rounded-to-Nearest
Integer
x
x
63-Bit Fraction
xxx…x00
xxx…x00
Guard
1
0
Round
0
0
Sticky
0
0
The least significant bit of the rounded result does not increment even though the guard
bit is set in the intermediate result. The IEEE 754 standard specifies that tie cases should
be handled in this manner. If the destination data format is extended and there is a
difference between the infinitely precise intermediate result and the round-to-nearest
result, the relative difference is 2^–64 (the value of the guard bit). This error is equal to one-
half of the least significant bit’s value and is the worst case error that can be introduced
when using the RN mode. Thus, the term one-half unit in the last place correctly identifies
the error bound for this operation. This error specification is the relative error present in
the result; the absolute error bound is equal to 2^exponent x 2^–64. The following example
illustrates the error bound for the other rounding modes:
Result
Intermediate
Rounded-to-Nearest
Integer
x
x
63-Bit Fraction
xxx…x00
xxx…x00
Guard
1
0
Round
1
0
Sticky
1
0
The difference between the infinitely precise result and the rounded result is 2 ^–64 + 2^–65 +
2^–66, which is slightly less than 2^–63 (the value of the least significant bit). Thus, the error
bound for this operation is not more than one unit in the last place. For all arithmetic
operations, the FPU meets these error bounds, providing accurate and repeatable results.
9.5 POSTPROCESSING OPERATION
Most operations end with a postprocessing step. The FPU provides two steps in
postprocessing. First, the condition code bits in the FPSR are set or cleared at the end of
each arithmetic operation or move operation to a single floating-point data register. The
condition code bits are consistently set based on the result of the operation. Second, the
FPU supports 32 conditional tests that allow floating-point conditional instructions to test
floating-point conditions in exactly the same way as the integer conditional instructions
test the integer condition codes. The combination of consistently set condition code bits
and the simple programming of conditional instructions gives the MC68040 a very flexible,
high-performance method of altering program flow based on floating-point results. While
reading the summary for each instruction, it should be assumed that an instruction
performs postprocessing unless the summary specifically states that the instruction does
not do so. The following paragraphs describe postprocessing in detail.
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M68040 USER’S MANUAL
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