MC68LC040RC25A Datasheet, PDF (207/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
C1
C2
C3
C4
C5
C6
BCLK
SC1, SC0
A31–A0
SIZ1, SIZ0
TT1, TT0
R/W
TS
MI
TA
D31–D0
MEMORY INHIBITED FROM RESPONDING
TA DRIVEN BY PROCESSOR
BR
BG
BB
AM_BR*
AM_BG_*
DATA WRITTEN BY ALTERNATE BUS MASTER
ALTERNATE MASTER
LONG-WORD WRITE
* AM indicates the alternate bus master.
PROCESSOR
Figure 7-43. Snooped Long-Word Write, Memory Inhibited
7.10 RESET OPERATION
An external device asserts the reset input signal (RSTI) to reset the processor. When
power is applied to the system, external circuitry should assert RSTI for a minimum of 10
BCLK cycles after V_CC is within tolerance. Figure 7-44 is a functional timing diagram of
the power-on reset operation, illustrating the relationships among V_CC, RSTI, mode
selects, and bus signals. The BCLK and PCLK clock signals are required to be stable by
the time V_CC reaches the minimum operating specification. The V_IH levels of the clocks
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M68040 USER’S MANUAL
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7-65