MC68LC040RC25A Datasheet, PDF (192/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
require a pullup resistor to maintain a logic-one level between bus master tenures. The
alternate bus master should negate these signals before three-stating to minimize rise
time of the signals and ensure that the processor recognizes the correct level on the next
BCLK rising edge. At the end of C3, the processor recognizes the bus grant and bus idle
conditions (BG asserted and BB negated) and assumes ownership of the bus by asserting
BB and immediately beginning a bus cycle during C4. During C6, the processor begins the
second bus cycle for the misaligned operand and negates BR since no other accesses are
pending. During C7, the external bus arbiter grants the bus back to the alternate bus
master that is waiting for the processor to relinquish the bus. The processor negates BB
and TIP before three-stating these and all other bus signals during C8. Finally, the
alternate bus master recognizes the bus grant and idle conditions at the end of C8 and is
able to resume bus activity during C9.
C1
C2
C3
C4
C5
C6
C7
C8
C9
BCLK
A31–A0
TRANSFER
ATTRIBUTES
TS
TIP
TA
D31–D0
BR
BG
BB
AM_BR*
AM_BG*
ALTERNATE
MASTER
*AM indicates the alternate bus master.
PROCESSOR
ALTERNATE
MASTER
Figure 7-32. Processor Bus Request Timing
7-50
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