MC68LC040RC25A Datasheet, PDF (35/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
Table 1-4. Instruction Set Summary
Opcode
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR
ASL, ASR
Bcc
BCHG
BCLR
BFCHG
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
BKPT
BRA
BSET
BSR
Operation
BCD Source + BCD Destination + X ø Destination
Source + Destination ø Destination
Source + Destination ø Destination
Immediate Data + Destination ø Destination
Immediate Data + Destination ø Destination
Source + Destination + X ø Destination
Source Λ Destination ø Destination
Immediate Data Λ Destination ø Destination
Source Λ CCR ø CCR
If supervisor state
then Source Λ SR ø SR
else TRAP
Destination Shifted by count ø Destination
If condition true
then PC + dn ø PC
~(bit number of Destination) ø Z;
~(bit number of Destination) ø (bit number) of
Destination
~(bit number of Destination) ø Z;
0 ø bit number of Destination
~(bit field of Destination) ø bit field of Destination
0 ø bit field of Destination
bit field of Source ø Dn
bit offset of Source ø Dn
bit offset of Source Bit Scan ø Dn
Dn ø bit field of Destination
1s ø bit field of Destination
bit field of Destination
Run breakpoint acknowledge cycle;
TRAP as illegal instruction
PC + dn ø PC
~(bit number of Destination) ø Z;
1 ø bit number of Destination
SP – 4 ø SP; PC ø (SP); PC + dn ø PC
Syntax
ABCD Dy,Dx
ABCD –(Ay),–(Ax)
ADD <ea>,Dn
ADD Dn,<ea>
ADDA <ea>,An
ADDI #<data>,<ea>
ADDQ #<data>,<ea>
ADDX Dy,Dx
ADDX –(Ay),–(Ax)
AND <ea>,Dn
AND Dn,<ea>
ANDI #<data>,<ea>
ANDI #<data>,CCR
ANDI #<data>,SR
ASd Dx,Dy1
ASd #<data>,Dy1
ASd <ea>1
Bcc <label>
BCHG Dn,<ea>
BCHG #<data>,<ea>
BCLR Dn,<ea>
BCLR #<data>,<ea>
BFCHG <ea>{offset:width}
BFCLR <ea>{offset:width}
BFEXTS <ea>{offset:width},Dn
BFEXTU <ea>{offset:width},Dn
BFFFO <ea>{offset:width},Dn
BFINS Dn,<ea>{offset:width}
BFSET <ea>{offset:width}
BFTST <ea>{offset:width}
BKPT #<data>
BRA <label>
BSET Dn,<ea>
BSET #<data>,<ea>
BSR <label>
1-14
M68040 USER’S MANUAL
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