MC68LC040RC25A Datasheet, PDF (50/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
SECTION 3
MEMORY MANAGEMENT UNIT
(EXCEPT MC68EC040 AND MC68EC040V)
NOTE
This section does not apply to the MC68EC040 and
MC68EC040V. Refer to Appendix B MC68EC040 for details.
All references to M68040 in this section only, refer to the
MC68040, MC68040V, and MC68LC040.
The M68040 supports a demand-paged virtual memory environment. Demand means that
programs request memory accesses through logical addresses, and paged means that
memory is divided into blocks of equal size, called page frames. Each page frame is
divided into pages of the same size. The operating system assigns pages to page frames
as they are required to meet the needs of the program.
The M68040 memory management includes the following features:
• Independent Instruction and Data Memory Management Units (MMUs)
• 32-Bit Logical Address Translation to 32-Bit Physical Address
• User-Defined 2-Bit Physical Address Extension
• Addresses Translated in Parallel with Indexing into Data or Instruction Cache
• 64-Entry Four-Way Set-Associative Address Translation Cache (ATC) for Each MMU
(128 Total Entries)
• Global Bit Allowing Flushes of All Nonglobal Entries from ATCs
• Selectable 4K or 8K Page Size
• Separate Supervisor and User Translation tables
• Two Independent Blocks for Each MMU Can Be Defined as Transparent
(Untranslated)
• Three-Level Translation Tables with Optional Indirection
• Supervisor and Write Protections
• History Bits Automatically Maintained in Descriptors
• External Translation Disable Input Signal (MDIS) for Emulator Support
• Caching Mode Selected on Page Basis
The MMUs completely overlap address translation time with other processing activities
when the translation is resident in one of the ATCs. ATC accesses operate in parallel with
MOTOROLA
M68040 USER'S MANUAL
3-1
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