MC68LC040RC25A Datasheet, PDF (148/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
Table 7-2. Summary of Access Types versus Bus Signal Encodings
Bus
Signal
Data Cache Normal
Push
Data/Code
Access
Access
Table
Search
Access
MOVE16
Access
Alternate
Interrupt
Breakpoint
Access Acknowledge Acknowledge
A31–A0
UPA1, UPA0
Access
Address
$0
SIZ1, SIZ0
TT1, TT0
L/Line
$0
Access
Address
MMU
Source ¹
B/W/L/Line
$0
Entry
Address
$0
Long Word
$0
Access
Address
MMU
Source ¹
Line
$1
Access
Address
$0
B/W/L
$2
$FFFFFFFF $00000000
$0
$0
Byte
$3
Byte
$3
TM4–TM2
TLN1, TLN0
R/ W
LOCK
LOCKE
$0
Cache Set
Entry
Write
Negated
$1,2,5, or 6 $3 or 4
$1 or 5
Cache Set
Entry2
Read/Write
Asserted/
Negated3
Undefined
Read/Write
Asserted/
Negated3
Undefined
Read/Write
Negated
Function
Code
Undefined
Int. Level $1–7
Undefined
Read/Write
Negated
Read
Negated
$0
Undefined
Read
Negated
CIOUT
Negated
MMU
Source ¹
Negated
MMU
Source ¹
Asserted
Negated
Negated
NOTES
1. The UPA1, UPA0, and CIOUT signals are determined by the U1, U0 data and CM bit fields, respectively,
corresponding to the access address.
2. The TLNx signals are defined only for normal push accesses and normal data line read accesses.
3. The LOCK signal is asserted during TAS, CAS, and CAS2 operand accesses and for some table search update
sequences. LOCKE is asserted for the last transfer of each locked sequence of transfers.
4. Refer to Section 5 Signal Description for definitions of the TMx signal encodings for normal, MOVE16,
and alternate accesses.
7.3 MISALIGNED OPERANDS
All M68040 data formats can be located in memory on any byte boundary. A byte operand
is properly aligned at any address; a word operand is misaligned at an odd address; and a
long word is misaligned at an address that is not evenly divisible by 4. However, since
operands can reside at any byte boundary, they can be misaligned. Although the M68040
does not enforce any alignment restrictions for data operands (including PC relative data
addressing), some performance degradation occurs when additional bus cycles are
required for long-word or word operands that are misaligned. For maximum performance,
data items should be aligned on their natural boundaries. All instruction words and
extension words must reside on word boundaries. Attempting to prefetch an instruction
word at an odd address causes an address error exception. Refer to Section 8 Exception
Processing for details on address error exceptions.
The M68040 data memory unit converts misaligned operand accesses that are
noncachable to a sequence of aligned accesses. These aligned accesses are then sent to
the bus controller for completion, always resulting in aligned bus transfers. Misaligned
operand accesses that miss in the data cache are cachable and are not aligned before
line filling. Refer to Section 4 Instruction and Data Caches for details on line fill and the
data cache.
7-6
M68040 USER’S MANUAL
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