MC68LC040RC25A Datasheet, PDF (7/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
TABLE OF CONTENTS (Continued)
Paragraph
Number
Title
Page
Number
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.5
5.5.1
5.5.2
5.6
5.6.1
5.6.2
5.6.3
5.7
5.7.1
5.7.2
5.7.3
5.8
5.8.1
5.8.2
5.8.3
5.9
5.9.1
5.9.2
5.9.3
5.10
5.11
5.12
5.12.1
5.12.2
5.12.3
5.12.4
5.12.5
5.13
5.14
Transfer in Progress (TIP) ................................................................. 5-8
Transfer Acknowledge (TA) ...............................................................5-8
Transfer Error Acknowledge (TEA) .................................................... 5-8
Transfer Cache Inhibit (TCI) .............................................................. 5-9
Transfer Burst Inhibit (TBI) ................................................................. 5-9
Snoop Control Signals...........................................................................5-9
Snoop Control (SC1, SC0) ................................................................ 5-9
Memory Inhibit (MI)............................................................................ 5-9
Arbitration Signals .................................................................................5-10
Bus Request (BR) ..............................................................................5-10
Bus Grant (BG) .................................................................................. 5-10
Bus Busy (BB)....................................................................................5-10
Processor Control Signals .....................................................................5-10
Cache Disable (CDIS)........................................................................ 5-10
Reset In (RSTI) .................................................................................. 5-11
Reset Out (RSTO)..............................................................................5-11
Interrupt Control Signals........................................................................5-11
Interrupt Priority Level (IPL2–IPL0).................................................... 5-11
Interrupt Pending Status (IPEND) ......................................................5-12
Autovector (AVEC) .............................................................................5-12
Status And Clock Signals ......................................................................5-12
Processor Status (PST3–PST0) ........................................................5-12
Bus Clock (BCLK) ..............................................................................5-14
Processor Clock (PCLK)—Not on MC68040V and MC68EC040V ... 5-14
MMU Disable (MDIS)—Not on MC68EC040 .........................................5-14
Data Latch Enable (DLE)—Only on MC68040...................................... 5-14
Test Signals ..........................................................................................5-15
Test Clock (TCK) ...............................................................................5-15
Test Mode Select (TMS) ....................................................................5-15
Test Data In (TDI) ..............................................................................5-15
Test Data Out (TDO) .........................................................................5-15
Test Reset (TRST)—Not on MC68040V and MC68EC040V............. 5-15
Power Supply Connections ................................................................... 5-15
Signal Summary ....................................................................................5-16
6.1
6.2
6.2.1
Section 6
IEEE 1149.1 Test Access Port (JTAG)
Overview ............................................................................................... 6-2
Instruction Shift Register .......................................................................6-3
EXTEST .............................................................................................6-3
MOTOROLA
M68040 USER’S MANUAL
ix
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