MC68LC040RC25A Datasheet, PDF (108/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
5.3.2 Transfer Modifier (TM2–TM0)
These three-state outputs provide supplemental information for each transfer type. Table
5-3 lists the encoding for normal and MOVE16 transfers, and Table 5-4 lists the encoding
for alternate access transfers. For interrupt acknowledge transfers, the TMx signals carry
the interrupt level being acknowledged; for breakpoint acknowledge transfers and
LPSTOP broadcast cycles on the MC68040V and MC68EC040V, the TMx signals are low.
When the M68040 is not the bus master, the TMx signals are set to a high-impedance
state.
Table 5-3. Normal and MOVE16 Access
Transfer Modifier Encoding
TM2
TM1
TM0
Transfer Modifier
0
0
0
Data Cache Push Access
0
0
1
User Data Access*
0
1
0
User Code Access
0
1
1
MMU Table Search Data Access
1
0
0
MMU Table Search Code Access
1
0
1
Supervisor Data Access*
1
1
0
Supervisor Code Access
1
1
1
Reserved
* MOVE16 accesses use only these encodings.
Table 5-4. Alternate Access Transfer Modifier Encoding
TM2
TM1
TM0
Transfer Modifier
0
0
0
Logical Function Code 0
0
0
1
Reserved
0
1
0
Reserved
0
1
1
Logical Function Code 3
1
0
0
Logical Function Code 4
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Logical Function Code 7
5.3.3 Transfer Line Number (TLN1, TLN0)
These three-state outputs indicate which line in the set of four data cache lines is being
accessed for normal push and line data read accesses. TLNx signals are undefined for all
other accesses to instruction space and are placed in a high-impedance state when the
processor relinquishes the bus.
5-6
M68040 USER’S MANUAL
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