MC68LC040RC25A Datasheet, PDF (273/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

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exception handler can report. When an operand error occurs, the OPERR bit is set in the
FPSR EXC byte.
Table 9-11. Possible Operand Errors Exceptions
Instruction
FADD
FDIV
FMOVE to B,W,or L
FMUL
FSQRT
FSUB
FACOS
FASIN
FATANH
FCOS
FGETEXP
FGETMAN
FLOG10
FLOG2
FLOGN
FLOGNP1
FMOD
FMOVE to P
FREM
FSCALE
FSGLDIV
FSGLMUL
FSIN
FSINCOS
FTAN
Condition Causing Operand Error
Native to MC68040
(+inf) + (–inf) or (–inf) + (+inf)
0 ÷ 0 or inf ÷ inf
Integer overflow where the source is nonsignaling NAN or +infinity.
One operand is 0 and other is +inf.
Source < 0 or ±inf.
(+inf) – (+inf) or (–inf) – (–inf)
Nonnative to MC68040
Source is ±inf, > +1, or < –1
Source is ±inf, > +1, or < –1
Source is > +1 or < –1
Source is ±inf
Source is ±inf
Source is ±inf
Source is < 0
Source is < 0
Source is < 0
Source is ≤ 1
Floating-point data register is ±inf or source is 0, other operand is not a NAN
Source exponent > 999 (decimal) or k-Factor > 17
Floating-point data register is ±inf or source is 0, other operand is not a NAN
Source is ±inf
0 ÷ 0 or inf ÷ inf
One operand is 0, other operand is inf
Source is ±inf
Source is ±inf
Source is ±inf
9.7.3.1 MASKABLE EXCEPTION CONDITIONS. All conditions apply as listed in Table
9-11, with the exception of the FMOVE to byte, word, or long-word case.
a. If the user OPERR exception handler is disabled, an extended-precision
nonsignaling NAN with all mantissa bits set is stored in the destination floating-point
data register. No exceptions are reported, and instruction execution proceeds
normally.
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M68040 USER’S MANUAL
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