MC68LC040RC25A Datasheet, PDF (299/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
10.3 CINV AND CPUSH INSTRUCTION TIMING
The following details the execution time for the CINV and CPUSH instructions used to
perform maintenance of the instruction and data caches. These two instructions sample
interrupt request (IPL≈) signals on every clock instead of at instruction boundaries. While
performing the actual cache invalidate operation, the execution unit stalls to allow previous
write-backs and any pending instruction prefetches to complete. The total time required to
execute a cache invalidate instruction is dependent on the previous instruction stream.
Execution time for this instruction is independent of the selected cache combination. The
CINV instructions interlock operation of the <ea> calculate and execution stages to
prevent a previous instruction from accessing the caches until the invalidate operation is
complete. Idle refers to the number of clocks required for all pending writes and instruction
prefetches to complete. Table 10-3 list the CINV timings.
Table 10-3. CINV Timing
Instruction
CINVL
CINVP
CINVA
Execution Time
9 + Idle
266 + Idle
9 + Idle
Execution time for the CPUSH instruction is dependent on several factors, such as the
number of dirty cache lines and the size of the resulting push (either long-word or line); the
overlapping operations within the data cache and the bus controller; the distribution of
dirty cache lines; and the number of wait states in the push access on the bus. The
interaction of these factors determines the total time required to execute a CPUSH
instruction.
Since the distribution of dirty data within the cache is entirely dependent on the nature of
the user’s code, it is impossible to provide an equation for execution time that works for all
code sequences. Table 10-4 provides baseline information indicating best and worst case
execution times for the three CPUSH instruction variants. Best case corresponds to a
cache containing no dirty entries, while the worst case corresponds to all lines dirty and
requiring line pushes. In Table 10-4, line refers to the number of clocks required in the
user’s system for a line transfer. Idle refers to the number of clocks required for all
pending writes and instruction prefetches to complete.
Table 10-4. CPUSH Best and Worst Case Timing
Instruction
CPUSHL
CPUSHP
CPUSHA
Best Case
6
Execution Time
Worst Case
6 + Line + Idle
267
11 + 256 × Line + Idle
10-8
M68040 USER’S MANUAL
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