MC68LC040RC25A Datasheet, PDF (172/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
RESET
OTHERWISE
SAMPLE AND SYNCHRONIZE
IPL2–IPL0
INTERRUPT LEVEL >I2–I0,
OR TRANSITION ON LEVEL 7
ASSERT IPEND
Figure 7-19. Interrupt Pending Procedure
The M68040 asserts IPEND when an interrupt request is pending. Figure 7-20 illustrates
the assertion of IPEND relative to the assertion of an interrupt level on the IPL≈ signals.
IPEND signals external devices that an interrupt exception will be taken at an upcoming
instruction boundary (following any higher priority exception). The IPEND signal negates
after the processor recognizes the internal interrupt acknowledge and can precede the
external interrupt acknowledge bus cycle.
BCLK
IPL2–IPL0
IPEND
IPLs RECOGNIZED
ASSERT IPEND
IPLs SYNCHRONIZED
COMPARE REQUEST WITH MASK IN SR
Figure 7-20. Assertion of IPEND
7-30
M68040 USER’S MANUAL
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