MC68LC040RC25A Datasheet, PDF (332/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
11.6 OUTPUT AC TIMING SPECIFICATIONS (See Figures 11-3 to 11-7)
25 MHz
Large ¹ Small2
33 MHz
Large ¹ Small2
40 Mhz
Large ¹ Small2
Num
Characteristic
Min Max Min Max Min Max Min Max Min Max Min Max Unit
113
BCLK to Address CIOUT, LOCK ,
LOCKE, R/ W, SIZx, TLN, TMx, TTx,
9
21
9
30 6.50 18 6.50 25 5.25 16 5.25 24 ns
UPAx Valid
12 ^{BCLK to Output Invalid}
(Output Hold)
9 — 9 — 6.50 — 6.50 — 5.25 — 5.25 — ns
13 BCLK to TS Valid
9 21 9 30 6.50 18 6.50 25 5.25 16 5.25 24 ns
14 BCLK to TIP Valid
184 BCLK to Data Out Valid
9 21 9 30 6.50 18 6.50 25 5.25 17 5.25 24 ns
9 23 9 32 6.50 20 6.50 27 5.25 18 5.25 26 ns
194 ^{BCLK to Data Out Invalid (Output}
Hold)
9 — 9 — 6.50 — 6.50 — 5.25 — 5.25 — ns
203,4 ^{BCLK to Output Low Impedance}
9 — 9 — 6.50 — 6.50 — 5.25 — 5.25 ^— ns
215 BCLK to Data-Out High Impedance 9 20 9 20 6.50 17 6.50 17 5.25 16 5.25 16 ns
263 ^{BCLK to Multiplexed}
Address Valid
19 31 19 40 14 26 14 33 13 25 13 32 ns
273,5 ^{BCLK to Multiplexed}
Address Driven
19 — 19 — 14 — 14 — 13 — 13 — ns
283,4,5 ^{BCLK to Multiplexed Address}
High Impedance
9 18 9 18 6.50 15 6.50 15 5.25 14 5.25 14 ns
294,5
304
BCLK to Multiplexed
Data Driven
BCLK to Multiplexed Data Valid
19 — 19 — 14 20 14 20 13 19 13 19 ns
19 33 19 42 14 28 14 35 13 27 13 34 ns
383
BCLK to Address, CIOUT , LOCK,
LOCKE, R/ W, SIZx, TS, TLNx, TMx,
9
18
9
18 6.50 15 6.50 15 5.25 14 5.25 14 ns
TTx, UPAx High Impedance
39 ^{BCLK to BB, TA, TIP}
High Impedance
19 28 19 28 14 23 14 23 11.5 22 11.5 22 ns
40 BCLK to BR , BB Valid
9 21 9 30 6.50 18 6.50 25 5.25 16 5.25 24 ns
43 BCLK to MI Valid
9 21 9 30 6.50 18 6.50 25 5.25 17 5.25 24 ns
48 BCLK to TA Valid
9 21 9 30 6.50 18 6.50 25 5.25 17 5.25 24 ns
50 BCLK to IPEND, PSTx, RSTO Valid 9 21 9 30 6.50 18 6.50 25 5.25 17 5.25 24 ns
NOTES:
1. Output timing is specified for a valid signal measured at the pin. Large buffer timing is specified driving a 50 Ω
transmission line with a length characterized by a 2.5-ns one-way propagation delay, terminated through 50 Ω to
2.5 V. Large buffer output impedance is 4–12 Ω, resulting in incident wave switching for this environment. All
large buffer outputs must be terminated to guarantee operation.
2. Small buffer timing is specified driving an unterminated 30 Ω transmission line with a length characterized by a
2.5 ns one-way propagation delay. Small buffer output impedance is typically 30 Ω; the small buffer specifications
include approximately 5 ns for the signal to propagate the length of the transmission line and back.
3. Timing specifications 11, 20, and 38 for address bus output timing apply when normal bus operation is selected.
Specifications 26, 27, and 28 should be used when the multiplexed bus mode of operation is enabled.
4. Timing specifications 18 and 19 for data bus output timing apply when normal bus operation is selected.
Specifications 28 and 29 should be used when the multiplexed bus mode of operation is enabled.
5. Timing specifications 21, 27, 28, and 29 are measured from BCLK edges. By design, the MC68040 cannot drive
address and data simultaneously during multiplexed operations.
11-4
M68040 USER’S MANUAL
MOTOROLA
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