MC68LC040RC25A Datasheet, PDF (75/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
3.3 ADDRESS TRANSLATION CACHES
The ATCs in the MMUs are four-way set-associative caches that each store 64 logical-to-
physical address translations and associated page information similar in form to the
corresponding page descriptors in memory. The purpose of the ATC is to provide a fast
mechanism for address translation by avoiding the overhead associated with a table
search of the logical-to-physical mapping of recently used logical addresses. Figure 3-20
illustrates the organization of the ATC.
31
16 12
0
F
C
PAGE FRAME
PAGE OFFSET
2
16
11
12
PAGE SIZE
17
MUX
13
SET
SELECT
4
SET 0 TAG
SET 1
•
•
•
SET 15 ^TAG
ENTRY
•
•
•
ENTRY
PA(11–0)
MUX ^PA(12)
1
PAGE SIZE ₁₉
PA(31–13)
9
STATUS
29
29
MUX
17
3
2
1
COMPARATOR
0
HIT 3
HIT 2
HIT 1
HIT 0
Figure 3-20. ATC Organization
LINE SELECT
HIT
HIT
DETECT
3-26
M68040 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA