MC68LC040RC25A Datasheet, PDF (209/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
For processor resets after the initial power-on reset, RSTI should be asserted for at least
10 clock periods. Figure 7-45 illustrates timings associated with a reset when the
processor is executing bus cycles. Note that BB and TIP (and TA if driven during a
snooped access) are negated before transitioning to a three-state level.
BCLK
RSTI
CDIS, MDIS,
IPL2–IPL0
BUS
SIGNALS
TS
TIP
BR
BG
BB
MI
t > 10
CLOCKS
2
CLOCKS
128
CLOCKS
Figure 7-45. Normal Reset Timing
Resetting the processor causes any bus cycle in progress to terminate as if TA or TEA
had been asserted. In addition, the processor initializes registers appropriately for a reset
exception. Section 8 Exception Processing describes exception processing. When a
RESET instruction is executed, the processor drives the reset out (RSTO) signal for 512
BCLK cycles. In this case, the processor resets the external devices of the system, and
the internal registers of the processor are unaffected. The external devices connected to
the RSTO signal are reset at the completion of the RESET instruction. An RSTI signal that
is asserted to the processor during execution of a RESET instruction immediately resets
the processor and causes the RSTO signal to negate. RSTO can be logically ANDed with
the external signal driving RSTI to derive a system reset signal that is asserted for both an
external processor reset and execution of a RESET instruction.
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M68040 USER’S MANUAL
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