MC68LC040RC25A Datasheet, PDF (146/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
31
24 23
16 15
87
0
REGISTER
BYTE 3
BYTE 2
BYTE 1
BYTE 0
MULTIPLEXER
ROUTING
EXTERNAL
DATA BUS
D31–D24
D23–D16
D15–D8
D7–D0
INTERNAL TO
THE MC68040
EXTERNAL BUS
31
ADDRESS
$xxxxxxx0
BYTE 3
24 23
BYTE 2
16 15
87
BYTE 1
Figure 7-3. Data Multiplexing
0
BYTE 0
Table 7-1 lists the combinations of the SIZx, A1, and A0 signals, collectively called byte
enable signals, that are used for each of the four sections of the data bus. In the table,
BYTEn indicates the data bus section that is active, the portion of the requested operand
that is read or written during that bus transfer. For line transfers, all bytes are valid as
listed and can correspond to portions of the requested operand or to data required to fill
the remainder of the cache line. The bytes labeled with a dash are not required; they are
ignored on read transfers and driven with undefined data on write transfers. Not selecting
these bytes prevents incorrect accesses in sensitive areas such as I/O devices. Figure 7-4
illustrates a logic diagram for one method for generating byte enable signals from the
SIZx, A1, and A0 and the associated PAL equation. These byte enable signals can be
combined with the address decode logic.
Table 7-1. Data Bus Requirements for Read and Write Cycles
Transfer
Size
Byte
Word
Long Word
Line
Signal Encodings
SIZ1 SIZ0 A1 A0
0
1
00
0
1
01
0
1
10
0
1
11
1
0
00
1
0
10
0
0
XX
1
1
XX
D31–D24
BYTEn
—
—
—
BYTEn
—
BYTEn
BYTEn
Active Data Bus Sections
D23–D16
D15–D8
—
BYTEn
—
—
—
—
BYTEn
—
BYTEn
—
—
BYTEn
BYTE n
BYTEn
BYTEn
BYTEn
D7–D0
—
—
—
BYTEn
—
BYTEn
BYTEn
BYTEn
7-4
M68040 USER’S MANUAL
MOTOROLA
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