MC68LC040RC25A Datasheet, PDF (51/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
indexing into the on-chip instruction and data caches. The MMU MDIS signal dynamically
disables address translation for emulation and diagnostic support.
Figure 3-1 illustrates the MMUs contained in the two memory units, one for instructions
(supporting instruction prefetches) and one for data (supporting all other accesses). Each
unit contains an MMU, main cache, and snoop controller. The corresponding MMUs
contain two transparent translation registers, which identify blocks of memory that can be
accessed without translation. The MMUs also contain control logic and corresponding
address translation caches (ATCs) in which recently used logical-to-physical address
translations are stored. The data memory unit contains a data write and data read buffer,
and the instruction memory unit contains an instruction line read buffer. These buffers
temporarily hold data until an opportune moment arises to write the data to external
memory or read the operand/instruction into the integer unit.
INSTRUCTION DATA BUS
CONVERT
EXECUTE
WRITE-
BACK
FLOATING-
POINT
UNIT
INSTRUCTION
FETCH
DECODE
EA
CALCULATE
EA
FETCH
EXECUTE
WRITE-
BACK
INTEGER
UNIT
INSTRUCTION
ATC
INSTRUCTION
CACHE
INSTRUCTION
MMU/CACHE/SNOOP
CONTROLLER
INSTRUCTION MEMORY UNIT
INSTRUCTION
ADDRESS
B
U
S
DATA MEMORY UNIT
DATA
MMU/CACHE/SNOOP
CONTROLLER
C
O
N
T
R
O
L
DATA
L
ADDRESS
E
R
ADDRESS
BUS
DATA
BUS
BUS
CONTROL
SIGNALS
DATA
ATC
DATA
CACHE
OPERAND DATA BUS
Figure 3-1. Memory Management Unit
The principal MMU function is to translate logical addresses to physical addresses using
translation tables stored in memory. As the MMU receives a logical address from the
integer unit, it searches its ATC for the corresponding physical address using the upper
3-2
M68040 USER'S MANUAL
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com