MC68LC040RC25A Datasheet, PDF (47/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

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31
15
0
A7 '(ISP)
INTERRUPT STACK POINTER
31
15
0
A7 "(MSP) MASTER STACK POINTER
15
7
0
(CCR)
SR
STATUS REGISTER
31
0
VBR
VECTOR BASE REGISTER
31
20
SFC
ALTERNATE SOURCE AND DESTINATION
DFC
FUNCTION CODE REGISTERS
31
0
CACR
CACHE CONTROL REGISTER
Figure 2-4. Integer Unit Supervisor Programming Model
The supervisor programming model consists of the registers available to the user as well
as the following control registers:
• Two 32-Bit Supervisor Stack Pointers (ISP, MSP)
• 16-Bit Status Register (SR)
• 32-Bit Vector Base Register (VBR)
• Two 32-Bit Alternate Function Code Registers: Source Function Code (SFC) and
Destination Function Code (DFC)
• 32-Bit Cache Control Register (CACR)
The following paragraphs describe the supervisor programming model registers.
Additional information on the ISP, MSP, SR, and VBR registers can be found in Section 8
Exception Processing.
2.2.2.1 INTERRUPT AND MASTER STACK POINTERS. In a multitasking operating
system, it is more efficient to have a supervisor stack pointer associated with each user
task and a separate stack pointer for interrupt-associated tasks. The M68040 provides two
supervisor stack pointers, master and interrupt. Explicit references to the SSP refer to
either the MSP or ISP while the processor is operating in the supervisor mode. All
instructions that use the SSP implicitly reference the active stack pointer. The ISP and
MSP are general-purpose registers and can be used as software stack pointers, index
registers, or base address registers. The ISP and MSP can be used for word and long-
word operations.
The M-bit of the SR selects whether the ISP or MSP is active. SSP references access the
ISP when the M-bit is clear, putting the processor into the interrupt mode. If an exception
being processed is an interrupt and the M-bit is set, the M-bit is cleared, putting the
processor into the interrupt mode. The interrupt mode is the default condition after reset,
and all SSP references access the ISP. The ISP can be used for interrupt control
information and for workspace area as interrupt exception handling requires.
SSP references access the MSP when the M-bit is set. The operating system uses the
MSP for each task pointing to a task-related area of supervisor data space. This
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M68040 USER’S MANUAL
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