MC68LC040RC25A Datasheet, PDF (331/442 Pages) Freescale Semiconductor, Inc – M68040 Users Manual

Freescale Semiconductor, Inc.
11.5 CLOCK AC TIMING SPECIFICATIONS (see Figure 11-1)
25 MHz
Num
Characteristic
Min Max
Frequency of Operation
20
25
1 PCLK Cycle Time
20
25
2 PCLK Rise Time
—
1.7
3 PCLK Fall Time
—
1.6
4 PCLK Duty Cycle Measured at 1.5 V
47.50 52.50
4a* PCLK Pulse Width High Measured at 1.5 V 9.50 10.50
4b* PCLK Pulse Width Low Measured at 1.5 V 9.50 10.50
5 BCLK Cycle Time
40
60
6,7 BCLK Rise and Fall Time
—
4
8 BCLK Duty Cycle Measured at 1.5 V
40
60
8a* BCLK Pulse Width High Measured at 1.5 V 16
24
8b* BCLK Pulse Width Low Measured at 1.5 V 16
24
9 PCLK, BCLK Frequency Stability
— 1000
10 PCLK to BCLK Skew
—
9
*Specification value at maximum frequency of operation.
33 MHz
Min Max
20
33
15
25
—
1.7
—
1.6
46.67 53.33
7
8
7
8
30
60
—
3
40
60
12
18
12
18
— 1000
—
n/a
40 MHz
Min Max
20
40
12.5 25
—
1.5
—
1.5
46.00 54.00
5.75 6.75
5.75 6.75
25
50
—
3
40
60
10
15
10
15
— 1000
—
n/a
Unit
MHz
ns
ns
ns
%
ns
ns
ns
ns
%
ns
ns
ppm
ns
PCLK
10
BCLK
1
4A
4B
VM
2
3
VIH
VIL
10
6
7
VM
VIH
VIL
8A
8B
5
Figure 11-1. Clock Input Timing Diagram
MOTOROLA
M68040 USER’S MANUAL
11-3
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