PIC18F97J60 Datasheet, PDF (85/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 5-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values on Details on
POR, BOR page:
T3CON
PSPCON⁽⁵⁾
RD16
IBF
T3CCP2
OBF
T3CKPS1 T3CKPS0
IBOV PSPMODE
T3CCP1
—
T3SYNC
—
TMR3CS
—
TMR3ON 0000 0000 60, 175
—
0000 ---- 61, 161
SPBRG1 EUSART1 Baud Rate Generator Register Low Byte
0000 0000 61, 306
RCREG1 EUSART1 Receive Register
0000 0000 61, 313
TXREG1 EUSART1 Transmit Register
xxxx xxxx 61, 315
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 61, 306
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 61, 306
EECON2 Program Memory Control Register (not a physical register)
---- ---- 61, 96
EECON1
IPR3
PIR3
PIE3
—
SSP2IP⁽⁵⁾
SSP2IF⁽⁵⁾
SSP2IE⁽⁵⁾
—
BCL2IP⁽⁵⁾
BCL2IF⁽⁵⁾
BCL2IE⁽⁵⁾
—
RC2IP⁽⁶⁾
RC2IF⁽⁶⁾
RC2IE⁽⁶⁾
FREE
TX2IP⁽⁶⁾
TX2IF⁽⁶⁾
TX2IE⁽⁶⁾
WRERR
TMR4IP
TMR4IF
TMR4IE
WREN
CCP5IP
CCP5IF
CCP5IE
WR
CCP4IP
CCP4IF
CCP4IE
—
CCP3IP
CCP3IF
CCP3IE
---0 x00-
1111 1111
0000 0000
0000 0000
61, 97
61, 132
61, 126
61, 129
IPR2
OSCFIP
CMIP
ETHIP
r
BCL1IP
—
TMR3IP
CCP2IP 1111 1-11 61, 131
PIR2
OSCFIF
CMIF
ETHIF
r
BCL1IF
—
TMR3IF
CCP2IF 0000 0-00 61, 125
PIE2
IPR1
PIR1
PIE1
MEMCON^(5,7)
OSCFIE
PSPIP⁽⁹⁾
PSPIF⁽⁹⁾
PSPIE⁽⁹⁾
EBDIS
OSCTUNE
TRISJ⁽⁶⁾
TRISH⁽⁶⁾
TRISG
PPST1
TRISJ7⁽⁵⁾
TRISH7⁽⁶⁾
TRISG7⁽⁵⁾
TRISF
TRISE
TRISD
TRISF7
TRISE7⁽⁶⁾
TRISD7⁽⁵⁾
CMIE
ADIP
ADIF
ADIE
—
PLLEN⁽⁸⁾
TRISJ6⁽⁵⁾
TRISH6⁽⁶⁾
TRISG6⁽⁵⁾
TRISF6
TRISE6⁽⁶⁾
TRISD6⁽⁵⁾
ETHIE
RC1IP
RC1IF
RC1IE
WAIT1
PPST0
TRISJ5⁽⁵⁾
TRISH5⁽⁶⁾
TRISG5⁽⁵⁾
TRISF5
TRISE5
TRISD5⁽⁵⁾
r
TX1IP
TX1IF
TX1IE
WAIT0
PPRE
TRISJ4⁽⁵⁾
TRISH4⁽⁶⁾
TRISG4
TRISF4
TRISE4
TRISD4⁽⁵⁾
BCL1IE
SSP1IP
SSP1IF
SSP1IE
—
—
TRISJ3⁽⁵⁾
TRISH3⁽⁶⁾
TRISG3⁽⁶⁾
TRISF3
TRISE3
TRISD3⁽⁵⁾
—
CCP1IP
CCP1IF
CCP1IE
—
—
TRISJ2⁽⁵⁾
TRISH2⁽⁶⁾
TRISG2⁽⁶⁾
TRISF2
TRISE2
TRISD2
TMR3IE
TMR2IP
TMR2IF
TMR2IE
WM1
—
TRISJ1⁽⁵⁾
TRISH1⁽⁶⁾
TRISG1⁽⁶⁾
TRISF1
TRISE1
TRISD1
CCP2IE
TMR1IP
TMR1IF
TMR1IE
WM0
—
TRISJ0⁽⁵⁾
TRISH0⁽⁶⁾
TRISG0⁽⁶⁾
TRISF0⁽⁵⁾
TRISE0
TRISD0
0000 0-00
1111 1111
0000 0000
0000 0000
0-00 --00
0000 ----
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
61, 128
61, 130
61, 124
61, 127
61, 106
61, 41
61, 159
61, 157
61, 155
61, 152
61, 150
61, 147
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0 1111 1111 61, 143
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0 1111 1111 61, 140
TRISA
LATJ⁽⁶⁾
LATH⁽⁶⁾
LATG
LATF
LATE
LATD
—
LATJ7⁽⁵⁾
LATH7⁽⁶⁾
LATG7⁽⁵⁾
LATF7
LATE7⁽⁶⁾
LATD7⁽⁵⁾
—
LATJ6⁽⁵⁾
LATH6⁽⁶⁾
LATG6⁽⁵⁾
LATF6
LATE6⁽⁶⁾
LATD6⁽⁵⁾
TRISA5
LATJ5⁽⁶⁾
LATH5⁽⁶⁾
LATG5⁽⁵⁾
LATF5
LATE5
LATD5⁽⁵⁾
TRISA4
LATJ4⁽⁶⁾
LATH4⁽⁶⁾
LATG4
LATF4
LATE4
LATD4⁽⁵⁾
TRISA3
LATJ3⁽⁵⁾
LATH3⁽⁶⁾
LATG3⁽⁶⁾
LATF3
LATE3
LATD3⁽⁵⁾
TRISA2
LATJ2⁽⁵⁾
LATH2⁽⁶⁾
LATG2⁽⁶⁾
LATF2
LATE2
LATD2
TRISA1
LATJ1⁽⁵⁾
LATH1⁽⁶⁾
LATG1⁽⁶⁾
LATF1
LATE1
LATD1
TRISA0
LATJ0⁽⁵⁾
LATH0⁽⁶⁾
LATG0⁽⁶⁾
LATF0⁽⁵⁾
LATE0
LATD0
--11 1111
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
61, 137
61, 159
61, 157
62, 155
62, 152
62, 150
62, 147
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0 xxxx xxxx 62, 143
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0 xxxx xxxx 62, 140
LATA
PORTJ⁽⁶⁾
PORTH⁽⁶⁾
PORTG
RDPU
RJ7⁽⁵⁾
RH7⁽⁶⁾
RG7⁽⁵⁾
REPU
RJ6⁽⁵⁾
RH6⁽⁶⁾
RG6⁽⁵⁾
LATA5
RJ5⁽⁶⁾
RH5⁽⁶⁾
RG5⁽⁵⁾
LATA4
RJ4⁽⁶⁾
RH4⁽⁶⁾
RG4
LATA3
RJ3⁽⁵⁾
RH3⁽⁶⁾
RG3⁽⁶⁾
LATA2
RJ2⁽⁵⁾
RH2⁽⁶⁾
RG2⁽⁶⁾
LATA1
RJ1⁽⁵⁾
RH1⁽⁶⁾
RG1⁽⁶⁾
LATA0
RJ0⁽⁵⁾
RH0⁽⁶⁾
RG0⁽⁶⁾
00xx xxxx
xxxx xxxx
0000 xxxx
111x xxxx
62, 137
62, 159
62, 157
62, 155
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends on condition, r = reserved bit, do not modify. Shaded cells
are unimplemented, read as ‘0’.
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
2: Bit 21 of the PC is only available in Serial Programming modes.
3: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
4: Alternate names and definitions for these bits when the MSSP module is operating in I²C™ Slave mode.
5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown
apply only to 100-pin devices.
6: These bits and/or registers are only available in 80-pin and 100-pin devices; in 64-pin devices, they are unimplemented and read as ‘0’. Reset
values are shown for 100-pin devices.
7: In Microcontroller mode, the bits in this register are unwritable and read as ‘0’.
8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’.
9: Implemented in 100-pin devices in Microcontroller mode only.
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 83