PIC18F97J60 Datasheet, PDF (255/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 18-8: SUMMARY OF REGISTERS ASSOCIATED WITH THE DMA CONTROLLER
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
Page
EIE
—
PKTIE DMAIE LINKIE TXIE
—
TXERIE RXERIE
63
EIR
—
PKTIF DMAIF LINKIF TXIF
—
TXERIF RXERIF
63
ECON1
TXRST RXRST DMAST CSUMEN TXRTS RXEN
—
—
60
ERXNDL Receive End Register Low Byte (ERXND<7:0>)
63
ERXNDH
—
—
— Receive End Register High Byte (ERXND<12:8>)
63
EDMASTL DMA Start Register Low Byte (EDMAST<7:0>)
63
EDMASTH
—
—
— DMA Start Register High Byte (EDMAST<12:8>)
63
EDMANDL DMA End Register Low Byte (EDMAND<7:0>)
63
EDMANDH
—
—
— DMA End Register High Byte (EDMAND<12:8>)
63
EDMADSTL DMA Destination Register Low Byte (EDMADST<7:0>)
63
EDMADSTH
—
—
— DMA Destination Register High Byte (EDMADST<12:8>)
63
EDMACSL DMA Checksum Register Low Byte (EDMACS<7:0>)
63
EDMACSH DMA Checksum Register High Byte (EDMACS<15:8>)
63
Legend: — = unimplemented. Shaded cells are not used.
18.10 Module Resets
The Ethernet module provides selective module
Resets:
• Transmit Only Reset
• Receive Only Reset
18.10.1 POWER-ON RESET (POR)
The Ethernet module uses the microcontroller’s
Power-on Reset pulse to start in the initialized state
when VDD is adequate for operation. A minimum rise
rate for VDD is specified (see Section 27.0 “Electrical
Characteristics”).
After a POR, the contents of the Ethernet buffer
memory will be unknown. All SFR and PHY registers
will be loaded with their specified Reset values. How-
ever, the PHY registers should not be accessed until
the PHY start-up timer has expired and the PHYRDY
bit (ESTAT<0>) becomes set, or at least 1 ms has
passed since the ETHEN bit is set. For more details,
see Section 18.1.3.1 “Start-up Timer”.
18.10.2 TRANSMIT ONLY RESET
The Transmit Only Reset is performed by writing a ‘1’
to the TXRST bit (ECON1<7>). This resets the transmit
logic only. Other register and control blocks, such as
buffer management and host interface, are not affected
by a Transmit Only Reset event. To return to normal
operation, the TXRST bit is cleared in software.
18.10.3 RECEIVE ONLY RESET
The Receive Only Reset is performed by writing a ‘1’ to
the RXRST bit (ECON1<6>). This action resets receive
logic only. Other register and control blocks, such as the
buffer management and host interface blocks, are not
affected by a Receive Only Reset event. To return to
normal operation, the RXRST bit is cleared in software.
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 253