PIC18F97J60 Datasheet, PDF (187/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 16-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
59
RCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
PIR3
PIE3
IPR3
TRISG
TMR1L
TMR1H
T1CON
TMR3H
TMR3L
IPEN
—
—
RI
TO
PD
POR
BOR
60
PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 61
PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 61
PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 61
OSCFIF CMIF ETHIF
r
BCL1IF
—
TMR3IF CCP2IF 61
OSCFIE CMIE ETHIE
r
BCL1IE
—
TMR3IE CCP2IE 61
OSCFIP CMIP ETHIP
r
BCL1IP
—
TMR3IP CCP2IP 61
SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 61
SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 61
SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 61
TRISG7 TRISG6 TRISG5 TRISG4 TRISG3⁽¹⁾ TRISG2 TRISG1 TRISG0
61
Timer1 Register Low Byte
60
Timer1 Register High Byte
60
RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 60
Timer3 Register High Byte
60
Timer3 Register Low Byte
60
T3CON
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 60
CCPR4L Capture/Compare/PWM Register 4 Low Byte
62
CCPR4H Capture/Compare/PWM Register 4 High Byte
62
CCPR5L Capture/Compare/PWM Register 5 Low Byte
63
CCPR5H Capture/Compare/PWM Register 5 High Byte
63
CCP4CON
—
—
DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 63
CCP5CON
—
—
DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 63
Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used by Capture/Compare, Timer1 or
Timer3.
Note 1: This bit is only available in 80-pin and 100-pin devices; otherwise, it is unimplemented and reads as ‘0’.
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 185