PIC18F97J60 Datasheet, PDF (156/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 10-15: PORTG FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RG0/ECCP3/ RG0⁽¹⁾
0
P3A⁽¹⁾
1
ECCP3⁽¹⁾
0
O
DIG LATG<0> data output.
I
ST PORTG<0> data input.
O
DIG CCP3 Compare and PWM output; takes priority over port data.
RG1/TX2/
CK2⁽¹⁾
1
P3A⁽¹⁾
0
RG1⁽¹⁾
0
1
TX2⁽¹⁾
1
CK2⁽¹⁾
1
I
ST CCP3 Capture input.
O
DIG ECCP3 Enhanced PWM output, channel A; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
O
DIG LATG<1> data output.
I
ST PORTG<1> data input.
O
DIG Synchronous serial data output (EUSART2 module); takes priority over
port data.
O
DIG Synchronous serial data input (EUSART2 module). User must configure
as an input.
RG2/RX2/
DT2⁽¹⁾
1
RG2⁽¹⁾
0
1
RX2⁽¹⁾
1
DT2⁽¹⁾
1
I
ST Synchronous serial clock input (EUSART2 module).
O
DIG LATG<2> data output.
I
ST PORTG<2> data input.
I
ST Asynchronous serial receive data input (EUSART2 module).
O
DIG Synchronous serial data output (EUSART2 module); takes priority over
port data.
1
RG3/CCP4/
RG3⁽¹⁾
0
P3D⁽¹⁾
1
CCP4⁽¹⁾
0
I
ST Synchronous serial data input (EUSART2 module). User must configure
as an input.
O
DIG LATG<3> data output.
I
ST PORTG<3> data input.
O
DIG CCP4 Compare output and CCP4 PWM output; takes priority over port data.
1
P3D⁽¹⁾
0
I
ST CCP4 Capture input.
O
DIG ECCP3 Enhanced PWM output, channel D; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RG4/CCP5/
RG4
0
O
DIG LATG<4> data output.
P1D
1
I
ST PORTG<4> data input.
CCP5
0
O
DIG CCP5 Compare output and CCP5 PWM output; takes priority over port data.
1
I
ST CCP5 Capture input.
RG5⁽²⁾
P1D
0
RG5⁽²⁾
0
O
DIG ECCP1 Enhanced PWM output, channel D; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
O
DIG LATG<0> data output.
RG6⁽²⁾
1
RG6⁽²⁾
0
I
ST PORTG<0> data input.
O
DIG LATG<0> data output.
RG7⁽²⁾
1
RG7⁽²⁾
0
I
ST PORTG<0> data input.
O
DIG LATG<0> data output.
1
I
ST PORTG<0> data input.
Legend:
Note 1:
2:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Implemented on 80-pin and 100-pin devices only.
Implemented on 100-pin devices only.
DS39762A-page 154
Advance Information
© 2006 Microchip Technology Inc.