PIC18F97J60 Datasheet, PDF (254/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

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After the DMA module has been initialized and has
begun its copy, one instruction cycle (TCY) will be
required for each byte copied. However, if the CPI core
executes a read or write instruction on the EDATA reg-
ister, or if the Ethernet receive hardware accumulates
one byte of data, the DMA will stall that cycle, yielding
to the higher priority operation. If a maximum size
1518-byte packet was copied while no other memory
bandwidth was being used, the DMA module would
require slightly more than 145.7 μs to complete at a
core frequency of 41.667 MHz. The time required to
copy a minimum size packet of 64 bytes would be
approximately 6.2 μs (at 41.667 MHz) plus register
configuration time.
18.9.2 CHECKSUM CALCULATIONS
The checksum calculation logic treats the source data
as a series of 16-bit big-endian integers. If the source
range contains an odd number of bytes, a padding byte
of 00h is effectively added to the end of the series for
purposes of calculating the checksum.
The calculated checksum is the 16-bit one’s
complement of the one’s complement sum of all 16-bit
integers. For example, if the bytes included in the
checksum were {89h, ABh, CDh}, the checksum would
begin by computing 89ABh + CD00h. A carry out of the
16th bit would occur in the example, so in 16-bit one’s
complement arithmetic, it would be added back to the
first bit. The resulting value of 56ACh would finally be
complemented to achieve a checksum of A953h.
To calculate a checksum:
1. Set the EDMAST and EDMAND register pairs to
point to the first and last bytes of buffer data to
be included in the checksum. Care should be
taken when programming these pointers to
prevent a never-ending checksum calculation
due to receive buffer wrapping.
2. To generate an optional interrupt when the
checksum calculation is done, set the DMAIE
(EIE<5>) and ETHIE (PIE2<5>) bits and clear
the DMAIF (EIR<5>) bit.
3. Start the calculation by setting the CSUMEN
(ECON1<4>) and DMAST (ECON1<5>) bits.
When the checksum is finished being calculated, the
hardware will clear the DMAST bit, set the DMAIF bit
and an interrupt will be generated if enabled. The DMA
Pointers will not be modified, and no memory will be
written to. The EDMACSH and EDMACSL registers will
contain the calculated checksum. The application may
write this value into a packet, compare this value with
zero (to validate a received block of data containing a
checksum field in it), or compare it with some other
checksum, such as a pseudo header checksum used in
various protocols (TCP, UDP, etc.).
Various protocols, such as TCP and IP, have a checksum
field inside a range of data which the checksum covers.
If a packet is received that requires checksum validation,
the user application can do the following:
1. Read the checksum from the packet and save it
to a temporary location.
2. Write zeros to the checksum field.
3. Calculate a new checksum using the DMA
controller.
4. Compare the results with the saved checksum
from step 1.
Writing to the receive buffer is permitted when the write
address is protected by means of the ERXRDPT Point-
ers. See Section 18.5.3 “Receiving Packets” for
additional information.
The IP checksum has unique mathematical properties
which may be used in some cases to reduce the
processing requirements further. Writing to the receive
buffer may be unnecessary in some applications.
When operating the DMA in Checksum mode, it takes
one instruction cycle (TCY) for every byte included in
the checksum. As a result, if a checksum over
1446 bytes was performed, the DMA module would
require slightly more than 138.8 μs to complete the
operation at 41.667 MHz.
At the same frequency, a small 20-byte header field
would take approximately 1.9s plus DMA setup time to
calculate a sum. These estimated times assume that
the Ethernet receive hardware does not need memory
access bandwidth and the CPU core does not issue
any reads or writes to the EDATA register while the
DMA is computing.
Like the DMA Copy mode, the checksum operation will
not start until the TXRTS bit (ECON1<3>) is clear. This
may considerably increase the checksum calculation
time if the application transmits a large packet and
immediately attempts to validate a checksum on a
received packet.
DS39762A-page 252
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© 2006 Microchip Technology Inc.