PIC18F97J60 Datasheet, PDF (447/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
FIGURE 27-20: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TXx/CKx
pin
RXx/DTx
pin
121
121
120
122
Note: Refer to Figure 27-3 for load conditions.
TABLE 27-24: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Max
120 TCKH2DTV SYNC XMIT (MASTER and SLAVE)
Clock High to Data Out Valid
—
40
121 TCKRF Clock Out Rise Time and Fall Time (Master mode)
—
20
122 TDTRF Data Out Rise Time and Fall Time
—
20
Units Conditions
ns
ns
ns
FIGURE 27-21: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TXx/CKx
pin
RXx/DTx
pin
125
126
Note: Refer to Figure 27-3 for load conditions.
TABLE 27-25: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min Max
125 TDTV2CKL SYNC RCV (MASTER and SLAVE)
Data Hold before CKx ↓ (DTx hold time)
10
—
126 TCKL2DTL Data Hold after CKx ↓ (DTx hold time)
15
—
Units
ns
ns
Conditions
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 445