PIC18F97J60 Datasheet, PDF (178/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
14.1 Timer3 Operation
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
cycle (FOSC/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
As with Timer1, the RC1/T1OSI and
RC0/T1OSO/T13CKI pins become inputs when the
Timer1 oscillator is enabled. This means the values of
TRISC<1:0> are ignored and the pins are read as ‘0’.
FIGURE 14-1:
TIMER3 BLOCK DIAGRAM
Timer1 Oscillator
Timer1 Clock Input
1
T1OSO/T13CKI
T1OSI
1
FOSC/4
Internal
Clock
0
T1OSCEN⁽¹⁾
TMR3CS
T3CKPS1:T3CKPS0
Prescaler
1, 2, 4, 8
2
Synchronize
Detect
0
Sleep Input
T3SYNC
TMR3ON
Timer3
On/Off
ECCPx Special Event Trigger
ECCPx Select from T3CON<6,3>
Clear TMR3
TMR3L
TMR3
High Byte
Set
TMR3IF
on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 Clock Input
1
T1OSO/T13CKI
T1OSI
1
FOSC/4
Internal
Clock
0
T1OSCEN⁽¹⁾
TMR3CS
T3CKPS1:T3CKPS0
T3SYNC
TMR3ON
Prescaler
1, 2, 4, 8
2
Synchronize
Detect
0
Sleep Input
Timer3
On/Off
ECCPx Special Event Trigger
ECCPx Select from T3CON<6,3>
Clear TMR3
TMR3L
TMR3
High Byte
8
Set
TMR3IF
on Overflow
Read TMR1L
Write TMR1L
8
8
TMR3H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39762A-page 176
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© 2006 Microchip Technology Inc.