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| PIC18F97J60 Datasheet, PDF (131/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet | |||
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PIC18F97J60 FAMILY
REGISTER 9-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0
SSP2IE(1)
bit 7
R/W-0
BCL2IE(1)
R-0
RC2IE(2)
R-0
TX2IE(2)
R/W-0
TMR4IE
R/W-0
CCP5IE
R/W-0
CCP4IE
R/W-0
CCP3IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
â1â = Bit is set
U = Unimplemented bit, read as â0â
â0â = Bit is cleared
x = Bit is unknown
bit 7
SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit(1)
1 = Enabled
0 = Disabled
bit 6
BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)(1)
1 = Enabled
0 = Disabled
bit 5
RC2IE: EUSART2 Receive Interrupt Enable bit(2)
1 = Enabled
0 = Disabled
bit 4
TX2IE: EUSART2 Transmit Interrupt Enable bit(2)
1 = Enabled
0 = Disabled
bit 3
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2
CCP5IE: CCP5 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
CCP4IE: CCP4 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0
CCP3IE: ECCP3 Interrupt Enable bit
1 = Enabled
0 = Disabled
Note 1: Implemented in 100-pin devices only.
2: Implemented in 80-pin and 100-pin devices only.
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 129
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