PIC18F97J60 Datasheet, PDF (324/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 20-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
59
PIR1
PSPIF
ADIF
RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
61
PIE1
PSPIE
ADIE
RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
61
IPR1
PIR3
PIE3
IPR3
PSPIP
ADIP
RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
61
SSP2IF BCL2IF RC2IF⁽¹⁾ TX2IF TMR4IF CCP5IF CCP4IF CCP3IF
61
SSP2IE BCL2IE RC2IE⁽¹⁾ TX2IE TMR4IE CCP5IE CCP4IE CCP3IE
61
SSP2IP BCL2IP RC2IP⁽¹⁾ TX2IP TMR4IP CCP5IP CCP4IP CCP3IP
61
RCSTAx
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
61
RCREGx EUSARTx Receive Register
61
TXSTAx
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
61
BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16
—
WUE ABDEN
62
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
62
SPBRGx EUSARTx Baud Rate Generator Register Low Byte
62
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: These bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as ‘0’.
20.4 EUSARTx Synchronous
Slave Mode
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTAx<7>). This mode differs from the
Synchronous Master mode in that the shift clock is sup-
plied externally at the CKx pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
20.4.1 EUSARTx SYNCHRONOUS
SLAVE TRANSMISSION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
If two words are written to the TXREGx and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREGx
register.
c) Flag bit, TXxIF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREGx register will transfer the second word
to the TSR and flag bit, TXxIF, will now be set.
e) If enable bit TXxIE is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
To set up a Synchronous Slave Transmission:
1. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If the signal from the CKx pin is to be inverted,
set the TXCKP bit. If the signal from the DTx pin
is to be inverted, set the RXDTP bit.
4. If interrupts are desired, set enable bit TXxIE.
5. If 9-bit transmission is desired, set bit TX9.
6. Enable the transmission by setting enable bit
TXEN.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
8. Start transmission by loading data to the
TXREGx register.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
DS39762A-page 322
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© 2006 Microchip Technology Inc.