PIC18F97J60 Datasheet, PDF (267/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

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19.4 I²C Mode
The MSSP module in I²C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCLx) – RC3/SCK1/SCL1 (or
RD6/SCK2/SCL2 for 100-pin devices)
• Serial data (SDAx) – RC4/SDI1/SDA1 (or
RD5/SDI2/SDA2 for 100-pin devices)
The user must configure these pins as inputs by setting
the TRISC<4:3> or TRISD<5:4> bits.
FIGURE 19-7:
MSSP BLOCK DIAGRAM
(I²C™ MODE)
Read
Internal
Data Bus
Write
SCLx
SDAx
SSPxBUF reg
Shift
Clock
SSPxSR reg
MSb
LSb
Match Detect
Address Mask
Addr Match
SSPxADD reg
Start and
Stop bit Detect
Set, Reset
S, P bits
(SSPxSTAT reg)
19.4.1 REGISTERS
The MSSP module has six registers for I²C operation.
These are:
• MSSP Control Register 1 (SSPxCON1)
• MSSP Control Register 2 (SSPxCON2)
• MSSP Status Register (SSPxSTAT)
• Serial Receive/Transmit Buffer Register
(SSPxBUF)
• MSSP Shift Register (SSPxSR) – Not directly
accessible
• MSSP Address Register (SSPxADD)
SSPxCON1, SSPxCON2 and SSPxSTAT are the
control and status registers in I²C mode operation. The
SSPxCON1 and SSPxCON2 registers are readable
and writable. The lower 6 bits of the SSPxSTAT are
read-only. The upper two bits of the SSPxSTAT are
read/write.
Many of the bits in SSPxCON2 assume different
functions, depending on whether the module is operat-
ing in Master or Slave mode; bits <5:1> also assume
different names in Slave mode. The different aspects of
SSPxCON2 are shown in Register 19-5 (for Master
mode) and Register 19-6 (Slave mode).
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data bytes
are written to or read from.
SSPxADD register holds the slave device address when
the MSSP is configured in I²C Slave mode. When the
MSSP is configured in Master mode, the lower seven
bits of SSPxADD act as the Baud Rate Generator reload
value.
In receive operations, SSPxSR and SSPxBUF together
create a double-buffered receiver. When SSPxSR
receives a complete byte, it is transferred to SSPxBUF
and the SSPxIF interrupt is set.
During transmission, the SSPxBUF is not
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 265