PIC18F97J60 Datasheet, PDF (231/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
18.3.1.1 Receive Error Interrupt (RXERIF)
The receive error interrupt is used to indicate a receive
buffer overflow condition. Alternately, this interrupt may
indicate that too many packets are in the receive buffer
and more cannot be stored without overflowing the
EPKTCNT register.
When a packet is being received and the receive buffer
runs completely out of space, or EPKTCNT is 255 and
cannot be incremented, the packet being received will
be aborted (permanently lost) and the RXERIF bit will
be set to ‘1’. Once set, RXERIF can only be cleared by
firmware or by a Reset condition. If the receive error
interrupt and Ethernet interrupt are enabled (both
RXERIE and ETHIE are set), an Ethernet interrupt is
generated. If the receive error interrupt is not enabled
(either RXERIE or ETHIE are cleared), the user appli-
cation may poll the RXERIF and take appropriate
action.
Normally, upon the receive error condition, the applica-
tion would process any packets pending from the
receive buffer and then make additional room for future
packets by advancing the ERXRDPT registers (low
byte first) and decrementing the EPKTCNT register.
See Section 18.5.3.3 “Freeing Receive Buffer
Space” for more information on processing packets.
Once processed, the application should clear the
RXERIF bit.
18.3.1.2 Transmit Error Interrupt (TXERIF)
The transmit error interrupt is used to indicate that a
transmit abort has occurred. An abort can occur
because of any of the following conditions:
1. Excessive collisions occurred as defined by the
Retransmission Maximum (RETMAX) bits in the
MACLCON1 register.
2. A late collision occurred as defined by the
Collision Window (COLWIN) bits in the
MACLCON2 register.
3. A collision after transmitting 64 bytes occurred
(LATECOL is set).
4. The transmission was unable to gain an oppor-
tunity to transmit the packet because the
medium was constantly occupied for too long.
The deferral limit was reached and the DEFER
bit (MACON4<6>) was clear.
5. An attempt to transmit a packet larger than the
maximum frame length defined by the MAMXFL
registers was made without setting the
HFRMEN bit (MACON3<2>) or per-packet
POVERRIDE and PHUGEEN bits.
Upon any of these conditions, the TXERIF flag is set to
‘1’. Once set, it can only be cleared by firmware or by a
Reset condition. If the transmit error interrupt is
enabled (TXERIE and ETHIE are both set), an Ethernet
interrupt is generated. If the transmit error interrupt is
not enabled (either TXERIE or ETHIE is cleared), the
application may poll TXERIF and take appropriate
action. Once the interrupt is processed, the flag bit
should be cleared.
After a transmit abort, the TXRTS bit will be cleared, the
TXABRT bit (ESTAT<1>) becomes set and the transmit
status vector will be written at ETXND + 1. The MAC
will not automatically attempt to retransmit the packet.
The application may wish to read the transmit status
vector and LATECOL bit to determine the cause of the
abort. After determining the problem and solution, the
application should clear the LATECOL (if set) and
TXABRT bits so that future aborts can be detected
accurately.
In Full-Duplex mode, condition 5 is the only one that
should cause this interrupt. Collisions and other prob-
lems related to sharing the network are not possible on
full-duplex networks. The conditions which cause the
transmit error interrupt meet the requirements of the
transmit interrupt. As a result, when this interrupt
occurs, TXIF will also be simultaneously set.
18.3.1.3 Transmit Interrupt (TXIF)
The transmit interrupt is used to indicate that the
requested packet transmission has ended (the TXRTS
bit has transitioned from ‘1’ to ‘0’). Upon transmission
completion, abort, or transmission cancellation by the
application, the TXIF flag will be set to ‘1’. If the
application did not clear the TXRTS bit, and the
TXABRT bit are not set, the packet was successfully
transmitted. Once TXIF is set, it can only be cleared in
software or by a Reset condition. If the transmit
interrupt is enabled (TXIE and ETHIE are both set), an
interrupt is generated. If the transmit interrupt is not
enabled (either TXIE or ETHIE is cleared), the
application may poll the TXIF bit and take appropriate
action.
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 229