PIC18F97J60 Datasheet, PDF (288/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

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19.4.7 BAUD RATE
In I²C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPxADD register (Figure 19-19). When a write
occurs to SSPxBUF, the Baud Rate Generator will
automatically begin counting. The BRG counts down to
0 and stops until another reload has taken place. The
BRG count is decremented twice per instruction cycle
(TCY) on the Q2 and Q4 clocks. In I²C Master mode, the
BRG is reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
Table 19-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.
19.4.7.1 Baud Rate and Module
Interdependence
Because MSSP1 and MSSP2 are independent, they
can operate simultaneously in I²C Master mode at
different baud rates. This is done by using different
BRG reload values for each module.
Because this mode derives its basic clock source from
the system clock, any changes to the clock will affect
both modules in the same proportion. It may be
possible to change one or both baud rates back to a
previous value by changing the BRG reload value.
FIGURE 19-19:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPxADD<6:0>
SSPM3:SSPM0
SCLx
Reload
Control
Reload
CLKO
BRG Down Counter
FOSC/4
TABLE 19-3: I²C™ CLOCK RATE w/BRG
Note 1:
FOSC
BRG Value
FSCL
(2 Rollovers of BRG)
41.667 MHz
19h
400 kHz⁽¹⁾
41.667 MHz
67h
31.25 MHz
13h
100 kHz
400 kHz⁽¹⁾
31.25 MHz
4Dh
20.833 MHz
09h
100 kHz
400 kHz⁽¹⁾
20.833 MHz
33h
100 kHz
The I²C™ interface does not conform to the 400 kHz I²C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
DS39762A-page 286
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© 2006 Microchip Technology Inc.