PIC18F97J60 Datasheet, PDF(206/474 Page) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

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PIC18F97J60 Datasheet, PDF (206/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

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PIC18F97J60 FAMILY

TABLE 17-5: REGISTERS ASSOCIATED WITH ECCP MODULES AND TIMER1 TO TIMER4

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

INTCON

RCON

PIR1

PIE1

IPR1

PIR2

PIE2

IPR2

PIR3

PIE3

IPR3

TRISB

TRISC

TRISD(1)

TRISE

TRISG

TRISH(2)

TMR1L

TMR1H

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE TMR0IF INT0IF

RBIF

59

IPEN

â

â

RI

TO

PD

POR

BOR

60

PSPIF

ADIF

RC1IF

TX1IF SSP1IF CCP1IF TMR2IF TMR1IF

61

PSPIE

ADIE

RC1IE

TX1IE SSP1IE CCP1IE TMR2IE TMR1IE

61

PSPIP

ADIP

RC1IP

TX1IP SSP1IP CCP1IP TMR2IP TMR1IP

61

OSCFIF CMIF

ETHIF

r

BCL1IF

â

TMR3IF CCP2IF

61

OSCFIE CMIE

ETHIE

r

BCL1IE

â

TMR3IE CCP2IE

61

OSCFIP CMIP

ETHIP

r

BCL1IP

â

TMR3IP CCP2IP

61

SSP2IF BCL2IF RC2IF

TX2IF TMR4IF CCP5IF CCP4IF CCP3IF

61

SSP2IE BCL2IE RC2IE

TX2IE TMR4IE CCP5IE CCP4IE CCP3IE

61

SSP2IP BCL2IP RC2IP

TX2IP TMR4IP CCP5IP CCP4IP CCP3IP

61

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

61

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

61

TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0

61

TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0

61

TRISG7(2) TRISG6(2) TRISG5(2) TRISG4 TRISG3(2) TRISG2(2) TRISG1(2) TRISG0(2)

61

TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0

61

Timer1 Register Low Byte

60

Timer1 Register High Byte

60

T1CON

RD16

T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

60

TMR2

Timer2 Register

60

T2CON

â T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 60

PR2

Timer2 Period Register

60

TMR3L

Timer3 Register Low Byte

60

TMR3H

Timer3 Register High Byte

60

T3CON

RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON

60

TMR4

Timer4 Register

62

T4CON

â T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 62

PR4

CCPRxL(3)

CCPRxH(3)

CCPxCON(3)

ECCPxAS(3)

ECCPxDEL(3)

Timer4 Period Register

Capture/Compare/PWM Register x Low Byte

Capture/Compare/PWM Register x High Byte

PxM1

PxM0 DCxB1 DCxB0

ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0

PxRSEN PxDC6 PxDC5 PxDC4

CCPxM3

PSSxAC1

PxDC3

CCPxM2

PSSxAC0

PxDC2

CCPxM1

PSSxBD1

PxDC1

CCPxM0

PSSxBD0

PxDC0

62

60

60

60

60, 63

63

Legend:

Note 1:

2:

3:

â = unimplemented, read as â0â, r = reserved. Shaded cells are not used during ECCP operation.

Applicable to 64-pin devices only.

Registers and/or specific bits are unimplemented on 64-pin devices.

Generic term for all of the identical registers of this name for all Enhanced CCP modules, where âxâ identifies the

individual module (ECCP1, ECCP2 or ECCP3). Bit assignments and Reset values for all registers of the same

generic name are identical.

DS39762A-page 204

Advance Information

Â© 2006 Microchip Technology Inc.

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