PIC18F97J60 Datasheet, PDF (60/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

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4.6 Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 4-1.
These bits are used in software to determine the nature
of the Reset.
Table 4-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
TABLE 4-1: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition
Program
Counter⁽¹⁾ _RI
RCON Register
TO PD POR
STKPTR Register
BOR STKFUL STKUNF
Power-on Reset
0000h
1
1
1
0
0
0
0
RESET Instruction
0000h
0
u
u
u
u
u
u
Brown-out Reset
0000h
1
1
1
u
0
u
u
MCLR during power-managed Run
0000h
u
1
u
u
u
u
u
modes
MCLR during power-managed Idle
0000h
u
1
0
u
u
u
u
modes and Sleep mode
WDT time-out during full power or
0000h
u
0
u
u
u
u
u
power-managed Run modes
MCLR during full power execution
0000h
u
u
u
u
u
u
u
Stack Full Reset (STVREN = 1)
0000h
u
u
u
u
u
1
u
Stack Underflow Reset
(STVREN = 1)
0000h
u
u
u
u
u
u
1
Stack Underflow Error (not an actual 0000h
u
u
u
u
u
u
1
Reset, STVREN = 0)
WDT time-out during power-managed PC + 2
u
0
0
u
u
u
u
Idle or Sleep modes
Interrupt exit from power-managed
PC + 2
u
u
0
u
u
u
u
modes
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
DS39762A-page 58
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© 2006 Microchip Technology Inc.