PIC18F97J60 Datasheet, PDF (220/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
To write to a PHY register:
1. Write the address of the PHY register to be
written to the MIREGADR register.
2. Write the lower 8 bits of data to write into the
MIWRL register.
3. Write the upper 8 bits of data to write into the
MIWRH register. Writing to this register auto-
matically begins the MII transaction, so it must
be written to after MIWRL. The BUSY bit is set
automatically.
The PHY register is written after the MII operation
completes, which takes 10.24 μs. When the write
operation has completed, the BUSY bit will clear itself.
The application should not start any MII scan or read
operations while busy.
When a PHY register is written to, the entire 16 bits is
written at once; selective bit writes are not imple-
mented. If it is necessary to reprogram only select bits
in the register, the controller must first read the PHY
register, modify the resulting data and then write the
data back to the PHY register.
The MAC can also be configured to perform automatic
back-to-back read operations on a PHY register. To
perform this scan operation:
1. Write the address of the PHY register to be
scanned into the MIREGADR register.
2. Set the MIISCAN bit (MICMD<1>). The scan
operation begins and the BUSY bit is set.
After MIISCAN is set, the NVALID (MISTAT<2>), SCAN
and BUSY bits are also set. The first read operation will
complete after 10.24 μs. Subsequent reads will be
done and the MIRDL and MIRDH registers will be con-
tinuously updated automatically at the same interval
until the operation is cancelled. The NVALID bit may be
polled to determine when the first read operation is
complete.
There is no status information which can be used to
determine when the MIRD registers are updated. Since
only one MII register can be read at a time, it must not
be assumed that the values of MIRDL and MIRDH
were read from the PHY at exactly the same time. In
Scan mode, the values of MIRDH and MIRDL are not
valid until NVALID has cleared. NVALID is cleared
automatically once the first read sequence is complete.
MIISCAN should remain set as long as the scan
operation is desired. The BUSY and SCAN bits are
automatically cleared after MIISCAN is set to ‘0’ and
the last read sequence is completed. MIREGADR
should not be updated while MIISCAN is set.
Starting new PHY operations, such as a read operation
or writing to the MIWRH register, must not be done
while a scan is underway. The operation can be
cancelled by clearing the MIISCAN bit and then polling
the BUSY bit. New operations may be started after the
BUSY bit is cleared.
DS39762A-page 218
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© 2006 Microchip Technology Inc.