PIC18F97J60 Datasheet, PDF (215/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
18.2.4 MAC AND MII REGISTERS
These SFRs are used to control the operations of the
MAC and, through the MIIM, the PHY. The MAC and
MII registers occupy data addresses E80h-E85h,
E8Ah, and EA0h through EB9h.
Although MAC and MII registers appear in the general
memory map of the microcontroller, these registers are
embedded inside the MAC module. Host interface logic
translates the microcontroller data/address bus data to
be able to access these registers. The Host interface
logic imposes restrictions on how firmware is able to
access the MAC and MII SFRs. See the following
notes.
Note 1: The MAC and MII SFRs can only be
accessed when the Ethernet module is
enabled, ETHEN (ECON2<5>) = 1).
2: Back to back accesses of MAC or MII
registers are not supported. Between any
instruction which addresses a MAC or MII
register, at least one NOP or other
instruction must be executed.
The three MACON registers control specific MAC oper-
ations and packet configuration operations. They are
shown in Register 18-4 through Register 18-6.
The MII registers are used to control the MIIM interface
and serves as the communication channel with the
PHY registers. They are shown in Register 18-7,
Register 18-8 and Register 18-9.
REGISTER 18-4: MACON1: MAC CONTROL REGISTER 1
U-0
—
bit 7
U-0
U-0
R-0
R/W-0
—
—
r
TXPAUS
R/W-0
RXPAUS
R/W-0
PASSALL
R/W-0
MARXEN
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
TXPAUS: Pause Control Frame Transmission Enable bit
1 = Allow the MAC to transmit pause control frames (needed for flow control in full duplex)
0 = Disallow pause frame transmissions
RXPAUS: Pause Control Frame Reception Enable bit
1 = Inhibit transmissions when pause control frames are received (normal operation)
0 = Ignore pause control frames which are received
PASSALL: Pass All Received Frames Enable bit
1 = Control frames received by the MAC will be written into the receive buffer if not filtered out
0 = Control frames will be discarded after being processed by the MAC (normal operation)
MARXEN: MAC Receive Enable bit
1 = Enable packets to be received by the MAC
0 = Disable packet reception
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 213