PIC18F97J60 Datasheet, PDF (189/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
The CCPRxH register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPRxH and 2-bit latch match TMR2
(TMR4), concatenated with an internal 2-bit Q clock or
2 bits of the TMR2 (TMR4) prescaler, the CCPx pin is
cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by Equation 16-3:
EQUATION 16-3:
( ) ^FOSC
PWM Resolution (max) = ^{log FPWM} bits
log(2)
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCPx pin will not be
cleared.
16.4.3 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 (PR4)
register.
2. Set the PWM duty cycle by writing to the
CCPRxL register and CCPxCON<5:4> bits.
3. Make the CCPx pin an output by clearing the
appropriate TRIS bit.
4. Set the TMR2 (TMR4) prescale value, then
enable Timer2 (Timer4) by writing to T2CON
(T4CON).
5. Configure the CCPx module for PWM operation.
TABLE 16-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
16
4
1
1
1
1
PR2 Value
FFh
FFh
FFh
3Fh
1Fh
17h
Maximum Resolution (bits)
10
10
10
8
7
6.58
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 187