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PIC18F97J60 Datasheet, PDF (253/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet
PIC18F97J60 FAMILY
18.9 Direct Memory Access Controller
The Ethernet module incorporates a dual purpose DMA
controller, which can be used to copy data between loca-
tions within the 8-Kbyte memory buffer. It can also be
used to calculate a 16-bit checksum which is compatible
with various industry standard communication protocols,
including TCP, UDP, IP, ICMP, etc.
The DMA is controlled using three pointers and a few
status/control bits:
• EDMASTH:EDMASTL – Source start address
• EDMANDH:EDMANDL – Source end address
• EDMADSTH:EDMADSTL – Destination start
address
• ECON1<DMAST> and ECON1<CSUMEN>
• EIR<DMAIF> and EIE<DMAIE>
The source and end pointers define what data will be
copied or checksumed. The destination pointer, used
only when copying data, defines where copied data will
be placed. All three pointers are with respect to the
8-Kbyte Ethernet memory and cannot be used to
access memory in the PIC® microcontroller data
memory space.
When a DMA operation begins, the EDMAST register
pair is copied into an internal source pointer. The DMA
will execute on one byte at a time and then increment
the internal source pointer. However, if a byte is pro-
cessed and the internal source pointer is equal to the
Receive Buffer End Pointer, ERXND, the source
pointer will not be incremented. Instead, the internal
source pointer will be loaded with the Receive Buffer
Start Pointer, ERXST. In this way, the DMA will follow
the circular FIFO structure of the receive buffer and
received packets can be processed using one opera-
tion. The DMA operation will end when the internal
source pointer matches the EDMAND Pointer.
While any DMA operation is in progress, the DMA Point-
ers and the CSUMEN bit (ECON1<4>) should not be
modified. The DMA operation can be canceled at any
time by clearing the DMAST bit (ECON1<5>). No regis-
ters will change; however, some memory bytes may
already have been copied if a DMA copy was in progress.
Some implementation considerations and firmware
requirements exist when using the DMA (see Note 1).
Note 1: If the EDMAND Pointers cannot be
reached because of the receive buffer
wrapping behavior, the DMA operation
will never end.
2: By design, the DMA module cannot be
used to copy or calculate a checksum over
only one byte (EDMAST = EDMAND). An
attempt to do so may overwrite all memory
in the buffer and never end.
3: After termination of a DMA operation
(DMAST is cleared by hardware or firm-
ware), firmware must not set DMAST
again within 4 instruction cycles.
18.9.1 COPYING MEMORY
To copy memory within the buffer:
1. Program the EDMAST, EDMAND, and
EDMADST register pairs with the appropriate
start, end and destination addresses. The
EDMAST registers should point to the first byte to
copy from, the EDMAND registers should point to
the last byte to copy and the EDMADST registers
should point to the first byte in the destination
range. The destination range will always be linear,
never wrapping at any values except from 8191 to
0 (the 8-Kbyte memory boundary). Extreme care
should be taken when calculating the End Pointer
to prevent a never ending DMA operation which
would overwrite the entire 8-Kbyte buffer.
2. If desired, set the DMAIE (EIE<5>) and ETHIE
(PIE2<5>) bits, and clear the DMAIF (EIR<5>)
flag bit to enable an interrupt at the end of the
copy process.
3. Clear the CSUMEN (ECON1<4>) bit.
4. Start the DMA copy by setting the DMAST
(ECON1<5>) bit.
If a transmit operation is in progress (TXRTS bit is set)
while the DMAST bit is set, the module will wait until the
transmit operation is complete before attempting to do
the DMA copy. This possible delay is required because
the DMA and transmission engine are unable to access
the buffer at the same time.
When the copy is complete, the DMA hardware will
clear the DMAST bit, set the DMAIF bit and generate
an interrupt (if enabled). The pointers and the
EDMACS registers will not be modified.
© 2006 Microchip Technology Inc.
Advance Information
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