PIC18F97J60 Datasheet, PDF (41/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
2.0 OSCILLATOR
CONFIGURATIONS
2.1 Overview
Devices in the PIC18F97J60 family incorporate an
oscillator and microcontroller clock system that differs
from standard PIC18FXXJXX devices. The addition of
the Ethernet module, with its requirement for a stable
25 MHz clock source, makes it necessary to provide a
primary oscillator that can provide this frequency, as
well as a range of different microcontroller clock
speeds. An overview of the oscillator structure is shown
in Figure 2-1.
Other oscillator features used in PIC18FXXJXX
enhanced microcontrollers, such as the internal RC
oscillator and clock switching, remain the same. They
are discussed later in this chapter.
2.2 Oscillator Types
The PIC18F97J60 family of devices can be operated in
five different oscillator modes:
1. HS
High-Speed Crystal/Resonator
2. HSPLL
3. EC
4. ECPLL
5. INTRC
High-Speed Crystal/Resonator
with Software PLL Control
External Clock with FOSC/4 Output
External Clock with Software PLL
Control
Internal 31 kHz Oscillator
2.2.1 OSCILLATOR CONTROL
The oscillator mode is selected by programming the
FOSC2:FOSC0 Configuration bits. FOSC1:FOSC0
bits select the default primary oscillator modes, while
FOSC2 selects when INTRC may be invoked.
The OSCCON register (Register 2-2) selects the active
clock mode. It is primarily used in controlling clock
switching in power-managed modes. Its use is discussed
in Section 2.7.1 “Oscillator Control Register”.
The OSCTUNE register (Register 2-1) is used to select
the system clock frequency from the primary oscillator
source by selecting combinations of prescaler/postscaler
settings and enabling the PLL. Its use is described in
Section 2.6.1 “PLL Block”.
FIGURE 2-1:
PIC18F97J60 FAMILY CLOCK DIAGRAM
OSC2
OSC1
Primary Oscillator
Sleep
PIC18F97J60 Family
PLL/Prescaler/Postscaler
PLL
Prescaler
5x PLL
PLL
Postscaler
Ethernet Clock
OSCTUNE<7:5>⁽¹⁾
Clock
Control
FOSC2:FOSC0
OSCCON<1:0>
T1OSO
T1OSI
Secondary Oscillator
T1OSCEN
Enable
Oscillator
INTRC
Source
EC, HS, ECPLL, HSPLL
T1OSC
Peripherals
Internal Oscillator
CPU
IDLEN
WDT, PWRT, FSCM
and Two-Speed Start-up
Clock Source Option
for other Modules
Note: See Table 2-2 for OSCTUNE register configurations and their corresponding frequencies.
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 39