PIC18F97J60 Datasheet, PDF (229/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
REGISTER 18-16: EIR: ETHERNET INTERRUPT REQUEST (FLAG) REGISTER
U-0
—
bit 7
R-0
PKTIF
R/C-0
DMAIF
R-0
LINKIF
R/C-0
TXIF
U-0
R/C-0
—
TXERIF
R/C-0
RXERIF
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6
PKTIF: Receive Packet Pending Interrupt Flag bit
1 = Receive buffer contains one or more unprocessed packets; cleared when PKTDEC is set
0 = Receive buffer is empty
bit 5
DMAIF: DMA Interrupt Flag bit
1 = DMA copy or checksum calculation has completed
0 = No DMA interrupt is pending
bit 4
LINKIF: Link Change Interrupt Flag bit
1 = PHY reports that the link status has changed; read PHIR register to clear
0 = Link status has not changed
bit 3
TXIF: Transmit Interrupt Flag bit
1 = Transmit request has ended
0 = No transmit interrupt is pending
bit 2
Unimplemented: Read as ‘0’
bit 1
TXERIF: Transmit Error Interrupt Flag bit
1 = A transmit error has occurred
0 = No transmit error has occurred
bit 0
RXERIF: Receive Error Interrupt Flag bit
1 = A packet was aborted because there is insufficient buffer space or the packet count is 255
0 = No receive error interrupt is pending
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 227