PIC18F97J60 Datasheet, PDF (28/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number _{Pin Buffer}
TQFP
Type Type
Description
RG0/ECCP3/P3A
RG0
ECCP3
P3A
PORTG is a bidirectional I/O port.
56
I/O
ST
Digital I/O.
I/O
ST
Capture 3 input/Compare 3 output/PWM 3 output.
O
—
ECCP3 PWM output A.
RG1/TX2/CK2
RG1
TX2
CK2
55
I/O
ST
Digital I/O.
O
—
EUSART2 asynchronous transmit.
I/O
ST
EUSART2 synchronous clock (see related RX2/DT2 pin).
RG2/RX2/DT2
RG2
RX2
DT2
42
I/O
ST
Digital I/O.
I
ST
EUSART2 asynchronous receive.
I/O
ST
EUSART2 synchronous data (see related TX2/CK2 pin).
RG3/CCP4/P3D
RG3
CCP4
P3D
41
I/O
ST
Digital I/O.
I/O
ST
Capture 4 input/Compare 4 output/PWM 4 output.
O
—
ECCP3 PWM output D.
RG4/CCP5/P1D
RG4
CCP5
P1D
10
I/O
ST
Digital I/O.
I/O
ST
Capture 5 input/Compare 5 output/PWM 5 output.
O
—
ECCP1 PWM output D.
Legend:
Note 1:
2:
3:
4:
TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
O
= Output
P = Power
OD
= Open-Drain (no P diode to VDD)
Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
DS39762A-page 26
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© 2006 Microchip Technology Inc.