PIC18F97J60 Datasheet, PDF (219/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

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18.2.5 PHY REGISTERS
The PHY registers provide configuration and control of
the PHY module, as well as status information about its
operation. All PHY registers are 16 bits in width.
There are a total of 32 PHY addresses; however, only
9 locations are implemented. Writes to unimplemented
locations are ignored and any attempts to read these
locations will return ‘0’. All reserved locations should be
written as ‘0’; their contents should be ignored when
read.
The implemented PHY registers are listed in
Table 18-2. The main PHY control registers are
described in Register 18-10 through Register 18-14.
The other PHY control and status registers are
described later in this chapter.
Thy PHY registers are only accessible through the MII
Management interface. They are not available to be
read or written to until the PHY start-up timer has
expired and the PHYRDY bit (ESTAT<0>) is set.
18.2.5.1 PHSTAT Registers
The PHSTAT1 and PHSTAT2 registers contain
read-only bits that show the current status of the PHY
module’s operations, particularly the conditions of the
communications link to the rest of the network.
The PHSTAT1 register (Register 18-11) contains the
LLSTAT bit; it clears and latches low if the physical
layer link has gone down since the last read of the
register. Periodic polling by the host controller can be
used to determine exactly when the link fails. It may be
particularly useful if the link change interrupt is not
used.
The PHSTAT1 register also contains a jabber status bit.
An Ethernet controller is said to be “jabbering” if it con-
tinuously transmits data without stopping and allowing
other nodes to share the medium. Generally, the jabber
condition indicates that the local controller may be
grossly violating the maximum packet size defined by
the IEEE specification. This bit latches high to indicate
that a jabber condition has occurred since the last read
of the register.
The PHSTAT2 register (Register 18-13) contains
status bits which report if the PHY module is linked to
the network and whether or not it is transmitting or
receiving.
18.2.5.2 PHID1 and PHID2 Registers
The PHID1 and PHID2 registers are read-only
registers. They hold constant data that help identify the
Ethernet controller and may be useful for debugging
purposes. This includes:
• The part number of the PHY module (PPN5:PPN0)
• The revision level of the PHY module
(PREV3:PREV0); and
• The PHY Identifier, as part of Microchip’s
corporate Organizationally Unique Identifier, OUI
(OUI3:OUI24)
The PHY part number and revision are part of PHID2.
The upper two bytes of the PHY identifier are located in
PHID1, with the remainder in PHID2. The exact
locations within registers are shown in Table 18-2.
Revision information is also stored in EREVID. This is
a read-only control register which contains a 5-bit
identifier for the specific silicon revision level of the
device.
18.2.5.3 Accessing PHY Registers
As already mentioned, the PHY registers exist in a
different memory space and are not directly accessible
by the microcontroller. Instead, they are addressed
through a special set of MII registers in the Ethernet
SFR bank, that implement a Media Independent
Interface Management (MIIM).
Access is similar to that of the Ethernet buffer, but uses
separate read and write buffers (MIRDH:MIRDL and
MIWRH:MIWRL) and a 5-bit address register
(MIREGADR). In addition, the MICMD and MISTAT
registers are used to control read and write operations.
To read from a PHY register:
1. Write the address of the PHY register to be read
from the MIREGADR register.
2. Set the MIIRD bit (MICMD<0>). The read
operation begins and the BUSY bit (MISTAT<0>)
is set.
3. Wait 10.24 μs, then poll the BUSY bit to be
certain that the operation is complete. When the
MAC has obtained the register contents, the
BUSY bit will clear itself. While BUSY is set, the
user application should not start any MIISCAN
operations or write to the MIWRH register.
4. Clear the MIIRD bit.
5. Read the entire 16 bits of the PHY register from
the MIRDL and MIRDH registers.
© 2006 Microchip Technology Inc.
Advance Information
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