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PIC18F97J60 Datasheet, PDF (22/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet | |||
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PIC18F97J60 FAMILY
TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTG is a bidirectional I/O port.
RG4/CCP5/P1D
RG4
CCP5
P1D
8
I/O
ST
Digital I/O.
I/O
ST
Capture 5 input/Compare 5 output/PWM 5 output.
O
â
ECCP1 PWM output D.
VSS
9, 25, 41, 56 P
â Ground reference for logic and I/O pins.
VDD
26, 38, 57
P
â Positive supply for peripheral digital logic and I/O pins.
AVSS
20
P
â Ground reference for analog modules.
AVDD
19
P
â Positive supply for analog modules.
ENVREG
18
I
ST Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
VCAP
10
Core logic power or external filter capacitor connection.
P
â
Positive supply for microcontroller core logic
(regulator disabled).
P
â
External filter capacitor connection (regulator enabled).
VSSPLL
55
P
â Ground reference for Ethernet PHY PLL.
VDDPLL
54
P
â Positive 3.3V supply for Ethernet PHY PLL.
VSSTX
52
P
â Ground reference for Ethernet PHY transmit subsystem.
VDDTX
49
P
â Positive 3.3V supply for Ethernet PHY transmit subsystem.
VSSRX
45
P
â Ground reference for Ethernet PHY receive subsystem.
VDDRX
48
P
â Positive 3.3V supply for Ethernet PHY receive subsystem.
RBIAS
53
P
â Bias current for Ethernet PHY. Must be tied to VSS via a resistor;
see Section 18.0 âEthernet Moduleâ for specification.
TPOUT+
51
O
â Ethernet differential signal output.
TPOUT-
50
O
â Ethernet differential signal output.
TPIN+
47
I Analog Ethernet differential signal input.
TPIN-
46
I Analog Ethernet differential signal input.
Legend:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
I = Input
P = Power
CMOS
Analog
O
OD
= CMOS compatible input or output
= Analog input
= Output
= Open-Drain (no P diode to VDD)
DS39762A-page 20
Advance Information
© 2006 Microchip Technology Inc.
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