PIC18F97J60 Datasheet, PDF (467/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
MISTAT (MII Status) ................................................ 216
OSCCON (Oscillator Control) .................................... 43
OSCTUNE (PLL Block Control) ................................. 41
PHCON1 (PHY Control 1) ........................................ 220
PHCON2 (PHY Control 2) ........................................ 222
PHIE (PHY Interrupt Enable) ................................... 228
PHIR (PHY Interrupt Request, Flag) ........................ 228
PHLCON (PHY Module LED Control) ...................... 224
PHSTAT1 (Physical Layer Status 1) ........................ 221
PHSTAT2 (Physical Layer Status 2) ........................ 223
PIE1 (Peripheral Interrupt Enable 1) ........................ 127
PIE2 (Peripheral Interrupt Enable 2) ........................ 128
PIE3 (Peripheral Interrupt Enable 3) ........................ 129
PIR1 (Peripheral Interrupt Request (Flag) 1) ........... 124
PIR2 (Peripheral Interrupt Request (Flag) 2) ........... 125
PIR3 (Peripheral Interrupt Request (Flag) 3) ........... 126
PSPCON (Parallel Slave Port Control) .................... 161
RCON (Reset Control) ....................................... 54, 133
RCSTAx (Receive Status and Control) .................... 303
SSPxCON1 (MSSPx Control 1, I²C Mode) .............. 267
SSPxCON1 (MSSPx Control 1, SPI Mode) ............. 257
SSPxCON2 (MSSPx Control 2, I²C
Master Mode) ................................................... 268
SSPxCON2 (MSSPx Control 2, I²C
Slave Mode) ..................................................... 269
SSPxSTAT (MSSPx Status, I²C Mode) ................... 266
SSPxSTAT (MSSPx Status, SPI Mode) .................. 256
STATUS ..................................................................... 87
STKPTR (Stack Pointer) ............................................ 72
T0CON (Timer0 Control) .......................................... 163
T1CON (Timer1 Control) .......................................... 167
T2CON (Timer2 Control) .......................................... 173
T3CON (Timer3 Control) .......................................... 175
T4CON (Timer4 Control) .......................................... 179
TXSTAx (Transmit Status and Control) ................... 302
WDTCON (Watchdog Timer Control) ...................... 353
RESET ............................................................................. 389
Reset .................................................................................. 53
Brown-out Reset (BOR) ............................................. 53
MCLR Reset, During Power-Managed Modes ........... 53
MCLR Reset, Normal Operation ................................ 53
Power-on Reset (POR) .............................................. 53
Stack Full Reset ......................................................... 53
Stack Underflow Reset .............................................. 53
State of Registers ...................................................... 58
Watchdog Timer (WDT) Reset ................................... 53
Resets .............................................................................. 345
Brown-out Reset (BOR) ........................................... 345
Oscillator Start-up Timer (OST) ............................... 345
Power-on Reset (POR) ............................................ 345
Power-up Timer (PWRT) ......................................... 345
RETFIE ............................................................................ 390
RETLW ............................................................................ 390
RETURN .......................................................................... 391
Return Address Stack ........................................................ 71
Return Stack Pointer (STKPTR) ........................................ 72
Revision History ............................................................... 455
RLCF ................................................................................ 391
RLNCF ............................................................................. 392
RRCF ............................................................................... 392
RRNCF ............................................................................ 393
S
SCKx ............................................................................... 255
SDIx ................................................................................. 255
SDOx ............................................................................... 255
SEC_IDLE Mode ............................................................... 50
SEC_RUN Mode ................................................................ 46
Serial Clock, SCKx .......................................................... 255
Serial Data In (SDIx) ........................................................ 255
Serial Data Out (SDOx) ................................................... 255
Serial Peripheral Interface. See SPI Mode.
SETF ............................................................................... 393
Slave Select (SSx) ........................................................... 255
SLEEP ............................................................................. 394
Sleep
OSC1 and OSC2 Pin States ...................................... 44
Software Simulator (MPLAB SIM) ................................... 410
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ........................................... 345
Special Function Registers ................................................ 79
Ethernet SFRs ........................................................... 80
Map ............................................................................ 79
SPI Mode (MSSP)
Associated Registers ............................................... 264
Bus Mode Compatibility ........................................... 263
Clock Speed and Module Interactions ..................... 263
Effects of a Reset .................................................... 263
Enabling SPI I/O ...................................................... 259
Master Mode ............................................................ 260
Master/Slave Connection ........................................ 259
Operation ................................................................. 258
Operation in Power-Managed Modes ...................... 263
Serial Clock ............................................................. 255
Serial Data In ........................................................... 255
Serial Data Out ........................................................ 255
Slave Mode .............................................................. 261
Slave Select ............................................................. 255
Slave Select Synchronization .................................. 261
SPI Clock ................................................................. 260
Typical Connection .................................................. 259
SSPOV ............................................................................ 290
SSPOV Status Flag ......................................................... 290
SSPSTAT Register
R/W Bit .................................................................... 272
SSPxSTAT Register
R/W Bit .................................................................... 270
SSx .................................................................................. 255
Stack Full/Underflow Resets .............................................. 73
SUBFSR .......................................................................... 405
SUBFWB ......................................................................... 394
SUBLW ............................................................................ 395
SUBULNK ........................................................................ 405
SUBWF ............................................................................ 395
SUBWFB ......................................................................... 396
SWAPF ............................................................................ 396
T
Table Pointer Operations (table) ........................................ 98
Table Reads/Table Writes ................................................. 73
TBLRD ............................................................................. 397
TBLWT ............................................................................ 398
2006 Microchip Technology Inc.
Advance Information
DS39762A-page 465