PIC18F97J60 Datasheet, PDF (161/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 10-19: PORTJ FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RJ0/ALE⁽¹⁾
RJ0⁽¹⁾
0
O
DIG LATJ<0> data output.
1
ALE⁽¹⁾
x
RJ1/OE⁽¹⁾
RJ1⁽¹⁾
0
1
OE⁽¹⁾
x
RJ2/WRL⁽¹⁾
RJ2⁽¹⁾
0
I
ST PORTJ<0> data input.
O
DIG External memory interface address latch enable control output; takes
priority over digital I/O.
O
DIG LATJ<1> data output.
I
ST PORTJ<1> data input.
O
DIG External memory interface output enable control output; takes priority
over digital I/O.
O
DIG LATJ<2> data output.
1
WRL⁽¹⁾
x
RJ3/WRH⁽¹⁾
RJ3⁽¹⁾
0
1
WRH⁽¹⁾
x
I
ST PORTJ<2> data input.
O
DIG External memory bus write low byte control; takes priority over
digital I/O.
O
DIG LATJ<3> data output.
I
ST PORTJ<3> data input.
O
DIG External memory interface write high byte control output; takes priority
over digital I/O.
RJ4/BA0
RJ4
0
1
BA0⁽²⁾
x
O
DIG LATJ<4> data output.
I
ST PORTJ<4> data input.
O
DIG External memory interface byte address 0 control output; takes priority
over digital I/O.
RJ5/CE
RJ6/LB⁽¹⁾
RJ5
0
O
DIG LATJ<5> data output.
1
I
ST PORTJ<5> data input.
CE⁽²⁾
x
O
DIG External memory interface chip enable control output; takes priority
over digital I/O.
RJ6⁽¹⁾
0
O
DIG LATJ<6> data output.
RJ7/UB⁽¹⁾
1
I
ST PORTJ<6> data input.
LB⁽¹⁾
x
O
DIG External memory interface lower byte enable control output; takes
priority over digital I/O.
RJ7⁽¹⁾
0
O
DIG LATJ<7> data output.
1
I
ST PORTJ<7> data input.
UB⁽¹⁾
x
O
DIG External memory interface upper byte enable control output; takes
priority over digital I/O.
Legend:
Note 1:
2:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Implemented on 100-pin devices only.
EMB functions are implemented on 100-pin devices only.
TABLE 10-20: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTJ
LATJ
TRISJ
RJ7⁽¹⁾ RJ6⁽¹⁾
LATJ7⁽¹⁾ LATJ6⁽¹⁾
TRISJ7⁽¹⁾ TRISJ6⁽¹⁾
RJ5
LATJ5
TRISJ5
RJ4
LATJ4
TRISJ4
RJ3⁽¹⁾
LATJ3⁽¹⁾
TRISJ3⁽¹⁾
RJ2⁽¹⁾
LATJ2⁽¹⁾
TRISJ2⁽¹⁾
RJ1⁽¹⁾
LATJ1⁽¹⁾
TRISJ1⁽¹⁾
RJ0⁽¹⁾
LATJ0⁽¹⁾
TRISJ0⁽¹⁾
PORTA
RJPU
—
RA5
RA4
RA3
RA2
RA1
RA0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTJ.
Note 1: Implemented on 100-pin devices only.
Reset
Values
on page
62
61
61
62
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 159