PIC18F97J60 Datasheet, PDF (147/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 10-9: PORTD FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RD0/AD0/PSP0 RD0
0
(RD0/P1B)
1
AD0⁽¹⁾
x
x
PSP0⁽¹⁾
x
O
DIG LATD<0> data output.
I
ST PORTD<0> data input.
O
DIG External memory interface, address/data bit 0 output.⁽²⁾
I
TTL External memory interface, data bit 0 input.⁽²⁾
O
DIG PSP read output data (LATD<0>); takes priority over port data.
x
P1B⁽³⁾
0
I
TTL PSP write data input.
O
DIG ECCP1 Enhanced PWM output, channel B; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RD1/AD1/PSP1 RD1
0
(RD1/ECCP3/
1
P3A)
AD1⁽¹⁾
x
x
PSP1⁽¹⁾
x
O
DIG LATD<1> data output.
I
ST PORTD<1> data input.
O
DIG External memory interface, address/data bit 1 output.⁽²⁾
I
TTL External memory interface, data bit 1 input.⁽²⁾
O
DIG PSP read output data (LATD<1>); takes priority over port data.
x
ECCP3⁽³⁾
0
I
TTL PSP write data input.
O
DIG ECCP3 Compare and PWM output; takes priority over port data.
1
P3A⁽³⁾
0
I
ST ECCP3 Capture input.
O
DIG ECCP3 Enhanced PWM output, channel A; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RD2/AD2/PSP2 RD2
0
(RD2/CCP4/
1
P3D)
AD2⁽¹⁾
x
x
PSP2⁽¹⁾
x
O
DIG LATD<2> data output.
I
ST PORTD<2> data input.
O
DIG External memory interface, address/data bit 2 output.⁽²⁾
I
TTL External memory interface, data bit 2 input.⁽²⁾
O
DIG PSP read output data (LATD<2>); takes priority over port data.
x
CCP4⁽³⁾
0
I
TTL PSP write data input.
O
DIG CCP4 Compare output and CCP4 PWM output; takes priority over port
data.
RD3/AD3/
PSP3⁽¹⁾
1
P3D⁽³⁾
0
RD3⁽¹⁾
0
1
AD3⁽¹⁾
x
x
PSP3⁽¹⁾
x
I
ST CCP4 Capture input.
O
DIG ECCP3 Enhanced PWM output, channel D; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
O
DIG LATD<3> data output.
I
ST PORTD<3> data input.
O
DIG External memory interface, address/data bit 3 output.⁽²⁾
I
TTL External memory interface, data bit 3 input.⁽²⁾
O
DIG PSP read output data (LATD<3>); takes priority over port data.
x
I
TTL PSP write data input.
Legend:
Note 1:
2:
3:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
These features or port pins are implemented only on 100-pin devices.
External memory interface I/O takes priority over all other digital and PSP I/O.
These features are implemented on this pin only on 64-pin devices; for all other devices, they are multiplexed with
RE6/RH7 (P1B), RG0 (ECCP3/P3A) or RG3 (CCP4/P3D).
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 145