PIC18F97J60 Datasheet, PDF (211/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

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18.2.1 ETHERNET BUFFER AND BUFFER
POINTER REGISTERS
The Ethernet buffer contains the transmit and receive
memory used by the Ethernet controller. The entire
buffer is 8 Kbytes, divided into separate receive and
transmit buffer spaces. The buffer is always accessible
through the EDATA and Ethernet Pointer SFRs,
regardless of whether or not the Ethernet module is
enabled. The sizes and locations of transmit and
receive memory are fully definable using the pointers in
the Ethernet SFR space.
18.2.1.1 Receive Buffer
The receive buffer constitutes a circular FIFO buffer
managed by hardware. The register pairs,
ERXSTH:ERXSTL and ERXNDH:ERXNDL, serve as
pointers to define the buffer’s size and location within
the memory. The byte pointed to by ERXST and the
byte pointed to by ERXND are both included in the
FIFO buffer.
As bytes of data are received from the Ethernet
interface, they are written into the receive buffer
sequentially. However, after the memory pointed to by
ERXND is written to, the hardware will automatically
write the next byte of received data to the memory
pointed to by ERXST. As a result, the receive hardware
will never write outside the boundaries of the FIFO.
The user may program the ERXST and ERXND
Pointers while the receive logic is disabled. The point-
ers must not be modified while the receive logic is
enabled; ERXEN (ECON1<2>) is set.
The ERXWRPTH:ERXWRPTL registers define a
location within the FIFO where the hardware will write
bytes that it receives. The pointer is read only and is
automatically updated by the hardware whenever a
new packet is received, depending on the hardware
filter settings. The pointer is useful for determining how
much free space is available within the FIFO.
The ERXRDPT registers define a location within the
FIFO where the receive hardware is forbidden to write
to. In normal operation, the receive hardware will write
data up to, but not including, the memory pointed to by
ERXRDPT. If the FIFO fills up with data and new data
continues to arrive, the hardware will not overwrite the
previously received data. Instead, the incoming data will
be thrown away and the old data will be preserved. In
order to continuously receive new data, the application
must periodically advance this pointer whenever it
finishes processing some, or all, of the old received data.
18.2.1.2 Transmit Buffer
Any space within the 8-Kbyte memory which is not
programmed as part of the receive FIFO buffer is consid-
ered to be the transmit buffer. The responsibility of
managing where packets are located in the transmit
buffer belongs to the application. Whenever the applica-
tion decides to transmit a packet, the ETXST and ETXND
Pointers are programmed with addresses specifying
where, within the transmit buffer, the particular packet to
transmit is located. The hardware does not check that the
start and end addresses do not overlap with the receive
buffer. To prevent buffer corruption, the firmware must not
transmit a packet while the ETXST and ETXND Pointers
are overlapping the receive buffer, or while the ETXND
Pointer is too close to the receive buffer. See
Section 18.5.2 “Transmitting Packets” for more
information.
18.2.1.3 Reading and Writing to the Buffer
The Ethernet buffer contents are accessed through the
EDATA register, which acts as a window from the
microcontroller data bus into the buffer. The location of
the window is determined by either the ERDPT or
EWRPT Pointers, depending on the operation being
performed. For example, writing to EDATA causes a
write to the Ethernet buffer at the address currently
indicated by EWRPTH:EWRPTL. Similarly, moving the
contents of EDATA to another register actually moves
the buffer contents at the address indicated by the
ERDPTH:ERDPTL registers.
Setting the AUTOINC bit (ECON2<7>) causes the
associated read or write pointer to increment by one
address following each read or write operation. This
eliminates the need to constantly update a pointer after
each read or write, simplifying multiple sequential
operations.
While sequentially reading from the receive buffer, a
wrapping condition will occur at the end of the receive
buffer. A read of EDATA from the address programmed
into the ERXNDH:ERXNDH registers will cause
ERDPTH:ERDPTL to be incremented to the value
contained in the ERXSTH:ERXSTL registers. While
sequentially writing to the buffer, no wrapping
conditions will occur.
18.2.1.4 DMA Access to the Buffer
The integrated DMA controller must read from the
buffer when calculating a checksum, and it must read
and write to the buffer when copying memory. The DMA
follows the same wrapping rules as previously
described. While it sequentially reads, it will be subject
to a wrapping condition at the end of the receive buffer.
All writes it does will not be subject to any wrapping
conditions. See Section 18.9 “Direct Memory
Access Controller” for more information.
© 2006 Microchip Technology Inc.
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