PIC18F97J60 Datasheet, PDF (213/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
18.2.2 SFRs AND THE ETHERNET
MODULE
Like other peripherals, direct control of the Ethernet
module is accomplished through a set of SFRs.
Because of their large number, the majority of these
registers are located in the bottom half of Bank 14 of
the microcontroller’s data memory space.
Five key SFRs for the Ethernet module are located in
the microcontroller’s regular SFR area in Bank 15,
where fast access is possible. They are:
• ECON1
• EDATA
• EIR
• The Ethernet Buffer Read Pointer pair (ERDPTH
and ERDPTL)
ECON1 is described along with other Ethernet control
registers in the following section. EDATA and
ERDPTH:ERDPTL are the Ethernet Data Buffer
registers and its pointers during read operations (see
Section 18.2.1 “Ethernet Buffer and Buffer Pointer
Registers”). EIR is part of the Ethernet interrupt
structure and is described in Section 18.3 “Ethernet
Interrupts”.
Many of the Ethernet SFRs in Bank 14 serve as pointer
registers to indicate addresses within the dedicated
Ethernet buffer for storage and retrieval of packet data.
Others store information for packet pattern masks or
checksum operations. Several are used for controlling
overall module operations, as well as specific MAC and
PHY functions.
18.2.3 ETHERNET CONTROL REGISTERS
The ECON1 register (Register 18-1) is used to control
the main functions of the module. Receive enable, trans-
mit request and DMA control bits are all located here.
The ECON2 register (Register 18-2) is used to control
other top level functions of the module. The ESTAT
register (Register 18-3) is used to report the high-level
status of the module and Ethernet communications.
The Ethernet SFRs with the ‘E’ prefix are always
accessible, regardless of whether or not the module is
enabled.
REGISTER 18-1: ECON1: ETHERNET CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
TXRST
RXRST
DMAST CSUMEN TXRTS
RXEN
—
bit 7
U-0
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
TXRST: Transmit Logic Reset bit
1 = Transmit logic is held in Reset
0 = Normal operation
RXRST: Receive Logic Reset bit
1 = Receive logic is held in Reset
0 = Normal operation
DMAST: DMA Start and Busy Status bit
1 = DMA copy or checksum operation is in progress (set by software, cleared by hardware or software)
0 = DMA hardware is idle
CSUMEN: DMA Checksum Enable bit
1 = DMA hardware calculates checksums
0 = DMA hardware copies buffer memory
TXRTS: Transmit Request to Send bit
1 = The transmit logic is attempting to transmit a packet (set by software, cleared by hardware or software)
0 = The transmit logic is idle
RXEN: Receive Enable bit
1 = Packets which pass the current filter configuration will be written into the receive buffer
0 = All packets received will be discarded by hardware
Unimplemented: Read as ‘0’
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 211