PIC18F97J60 Datasheet, PDF (192/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

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17.1 ECCP Outputs and Configuration
Each of the Enhanced CCP modules may have up to
four PWM outputs, depending on the selected
operating mode. These outputs, designated PxA
through PxD, are multiplexed with various I/O pins.
Some ECCPx pin assignments are constant, while
others change based on device configuration. For
those pins that do change, the controlling bits are:
• CCP2MX Configuration bit (80-pin and100-pin
devices only)
• ECCPMX Configuration bit (80-pin and100-pin
devices only)
• Program memory operating mode set by the EMB
Configuration bits (100-pin devices only)
The pin assignments for the Enhanced CCP modules
are summarized in Table 17-1, Table 17-2 and
Table 17-3. To configure the I/O pins as PWM outputs,
the proper PWM mode must be selected by setting the
PxMx and CCPxMx bits (CCPxCON<7:6> and <3:0>,
respectively). The appropriate TRIS direction bits for
the corresponding port pins must also be set as
outputs.
17.1.1 ECCP1/ECCP3 OUTPUTS AND
PROGRAM MEMORY MODE
In 100-pin devices, the use of Extended Microcontroller
mode has an indirect effect on the ECCP1 and ECCP3
pins in Enhanced PWM modes. By default, PWM
outputs P1B/P1C and P3B/P3C are multiplexed to
PORTE pins, along with the high-order byte of the
external memory bus. When the bus is active in
Extended Microcontroller mode, it overrides the
Enhanced CCP outputs and makes them unavailable.
Because of this, ECCP1 and ECCP3 can only be used
in compatible (single-output) PWM modes when the
device is in Extended Microcontroller mode and default
pin configuration.
An exception to this configuration is when a 12-bit
address width is selected for the external bus
(EMB1:EMB0 Configuration bits = 10). In this case, the
upper pins of PORTE continue to operate as digital I/O,
even when the external bus is active. P1B/P1C and
P3B/P3C remain available for use as Enhanced PWM
outputs.
If an application requires the use of additional PWM
outputs during Extended Microcontroller mode, the
P1B/P1C and P3B/P3C outputs can be reassigned to
the upper bits of PORTH. This is done by clearing the
ECCPMX Configuration bit.
17.1.2 ECCP2 OUTPUTS AND PROGRAM
MEMORY MODES
For 100-pin devices, the program memory mode of the
device (Section 5.1.3 “PIC18F9XJ60/9XJ65 Program
Memory Modes”) also impacts pin multiplexing for the
module.
The ECCP2 input/output (ECCP2/P2A) can be multi-
plexed to one of three pins. The default assignment
(CCP2MX Configuration bit is set) for all devices is
RC1. Clearing CCP2MX reassigns ECCP2/P2A to
RE7.
An additional option exists for 100-pin devices. When
these devices are operating in Microcontroller mode,
the multiplexing options described above still apply. In
Extended Microcontroller mode, clearing CCP2MX
reassigns ECCP2/P2A to RB3.
17.1.3 USE OF CCP4 AND CCP5 WITH
ECCP1 AND ECCP3
Only the ECCP2 module has four dedicated output pins
that are available for use. Assuming that the I/O ports
or other multiplexed functions on those pins are not
needed, they may be used without interfering with any
other CCP module.
ECCP1 and ECCP3, on the other hand, only have
three dedicated output pins: ECCPx/PxA, PxB and
PxC. Whenever these modules are configured for
Quad PWM mode, the pin normally used for CCP4 or
CCP5 becomes the PxD output pin for ECCP3 and
ECCP1, respectively. The CCP4 and CCP5 modules
remain functional but their outputs are overridden.
17.1.4 ECCP MODULES AND TIMER
RESOURCES
Like the standard CCP modules, the ECCP modules
can utilize Timers 1, 2, 3 or 4, depending on the mode
selected. Timer1 and Timer3 are available for modules
in Capture or Compare modes, while Timer2 and
Timer4 are available for modules in PWM mode.
Additional details on timer resources are provided in
Section 16.1.1 “CCP Modules and Timer
Resources”.
DS39762A-page 190
Advance Information
© 2006 Microchip Technology Inc.