PIC18F97J60 Datasheet, PDF (155/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
10.8 PORTG, TRISG and
LATG Registers
Depending on the particular device, PORTG is
implemented as a bidirectional port in one of three
ways:
• 64-pin devices: 1 bit wide (RG<4>)
• 80-pin devices: 5 bits wide (RG<4:0>)
• 100-pin devices: 8 bits wide (RG<7:0>)
The corresponding data direction register is TRISG.
Setting a TRISG bit (= 1) will make the corresponding
PORTG pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISG
bit (= 0) will make the corresponding PORTG pin an
output (i.e., put the contents of the output latch on the
selected pin). All pins on PORTG are digital only and
tolerate voltages up to 5.5V.
The Data Latch register (LATG) is also memory
mapped. Read-modify-write operations on the LATG
register read and write the latched output value for
PORTG.
PORTG is multiplexed with EUSART2 functions on
80-pin and 100-pin devices (Table 10-15). PORTG pins
have Schmitt Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings. The pin override value is not loaded into
the TRIS register. This allows read-modify-write of the
TRIS register without concern due to peripheral
overrides.
EXAMPLE 10-7: INITIALIZING PORTG
CLRF
CLRF
MOVLW
MOVWF
PORTG
LATG
04h
TRISG
; Initialize PORTG by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 153